Altera Qsys Generated Pci Express Wrapping

[emrelevent]

I have problem with pci express avalon busses. Altera's ip core has may input output on generated module. I didnt figure out how to drive all those io.
My board has following pci express signals,
PCIE_PERST_N PCIE_REFCLK_P PCIE_RX_P PCIE_TX_P PCIE_WAKE_N
And i only need tx_en, tx_data, tx_busy, rx_en,rx_data.
How can i wrap qsys generated module?
Thanks.

 

[K-J]

I have problem with pci express avalon busses. Altera's ip core has may input output on generated module. I didnt figure out how to drive all those io.
My board has following pci express signals,
PCIE_PERST_N PCIE_REFCLK_P PCIE_RX_P PCIE_TX_P PCIE_WAKE_N
And i only need tx_en, tx_data, tx_busy, rx_en,rx_data.
How can i wrap qsys generated module?
Thanks.

What did the User's Guide for the core have to say?