Altera DDR2 Controller Core

[param]

Hi All,
I am using the ddr2 core generated through MegaWizard function from Altera Quartus II. Please help and let me know if any one have earlier experience in using it. I need some support in simulating it.
Thanks

 

[odeafeiner]

we did it both with simulation and in the board. megawizard have one testbench.
just run as it said.

 

[param]

Hi
I have followed the document generated from the core wizard. But i could not get the result for read operation[read data is in Z - state]. I have instantiated the micron memory model in the generated testbench. Will you please guide me in simulating it and the things to be taken care for simulation as well as board level.
Which memory model you have used as DDR2?

 

[odeafeiner]

hi,

I don't think there is special thing. I also use micron model though
our board use different. you should set the board related timing when
you generate IP (I also tune them in the board test).

The thing I though is that the clock setting is same with your IP setting.
the read latency is consistent with the IP also. The Micron model have
some different parameters for different model in one file.

You can try it. and If you want, you can sent me the project.

regards,

 

[param]

Hi,
thanks for the reply. Now, i could simulate the core properly, i had to instantiate the memory model twice in my application, which solved the simulation isuue. Please can you guide me how to control the speed of the read/write. I have to set the memory clock while generating the core. But i have to write slower and read faster. How could i achieve different write and read speed using the core. I didnot find in the core-document regarding speed settings for read and write operations.

Thanks