All digital Receivers- Symbol Timing recovery

[moorthi]

Hi All
I'm Moorthi and I'd be thankful if my following query is answered.

I'm in the process of design and development of effcient method for symbol timing recovery for data rates greater than 512Kbps and upto 32Mbps. I'd like to implement the method which is not using PLL or DPLL. The idea is to use constant sampling rate at the receiver and then use the interpolation filters to estmate the errors and then feedback the error to the interpolater and get the timing.

If there are any other efficient method to achieve this plaese tell me the references of the same

Thank you in advance

--moorthi

 

[echo47]

Maybe you can find something useful in one of these Xilinx application notes:

Data Recovery:
**broken link removed**

High Speed Data Recovery Using Asynchronous Data Capture Techniques:
**broken link removed**

Dynamic Phase Alignment Using Asynchronous Data Capture:
**broken link removed**

 

[moorthi]

Hi
Thank you for the reply and the materials.

The materials you sent are related to direct implementation using delay elements and as for as the theory is concerned it not that much efficient since the lookup tables and the calculationa are more. I'm looking at the solutions using multirate dsps.

Pl help me in this

--moorthi