kwooks21
Newbie level 2
Hi!
I'm designing a digital delta-sigma modulator for fractional-n PLL.
Designing MASH is straghtforward, but sigle-loop is very difficult to me. Regarding single-loop, I found that a digital code conversion logic is required in the feedback path. Also, I found a paper which includes detail logic descriptions, but I couldn't understand that clearly.
And, I want to design single-loop with multi-bit quantizer. In this case, how can I code the feedback digital wards? For example, I tried to do digital logic level simulation of Ph.D Rhee's single-loop DSM in Matlab Simulink. But I have failed. Show me the way please...
Paper titles are...
1. Reduced complexity 1-bit high-order digital deltasigma modulator for low-voltage fractional-N frequency synthesis applications
2. W. Rhee, A. Ali, and B. Song, "A 1.1GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order delta-sigma modulator," ISSCC'00, pp. 198--199.
- You can easily find the 2nd paper. But for the 1st one, you need to use ieee ixplore.
I'm designing a digital delta-sigma modulator for fractional-n PLL.
Designing MASH is straghtforward, but sigle-loop is very difficult to me. Regarding single-loop, I found that a digital code conversion logic is required in the feedback path. Also, I found a paper which includes detail logic descriptions, but I couldn't understand that clearly.
And, I want to design single-loop with multi-bit quantizer. In this case, how can I code the feedback digital wards? For example, I tried to do digital logic level simulation of Ph.D Rhee's single-loop DSM in Matlab Simulink. But I have failed. Show me the way please...
Paper titles are...
1. Reduced complexity 1-bit high-order digital deltasigma modulator for low-voltage fractional-N frequency synthesis applications
2. W. Rhee, A. Ali, and B. Song, "A 1.1GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order delta-sigma modulator," ISSCC'00, pp. 198--199.
- You can easily find the 2nd paper. But for the 1st one, you need to use ieee ixplore.
