-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity my_entity is
port (
clk : in STD_LOGIC := 'X';
reset : in STD_LOGIC := 'X';
output1 : out STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );
output2 : out STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );
input1 : in STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );