[AHB] How connect Memory?

[ivlsi]

Hi All,

How to connect Memory to AHB bus?

AHB bus has two phases - Address and then Data on both Read and Write. How to cope?

Thank you!

 

[ads-ee]

1. decode address if it matches memory address space then keep going otherwise ignore the bus transaction
2. apply address to memory
3. for a write:
3a. apply data to memory
3b. strobe write to memory
4. for a read:
4a. capture read data from memory
4b. return read data on AHB bus.

Pretty much the same procedure for any bus.

 

[ivlsi]

Write Address is shifter related to Write Data by one clock cycle. So, it should be sampled before applying to Memory?

BTW, why Write Access on AHB bus is done with two phases (cycles) - Address/Controls and only then Data?

Are there any special bus lines for Memory in AHB bus (besides HRESP)?

 

[sharath666]

AHB is a 2 phase operation. This allows easy pipelining. The first data and the 2nd address can be sent out simultaneously. Similarly the 2nd data and 3rd address can be sent out at the same time.
I don't know of any special lines for memory in AHB as it is a very generic protocol. It can be used for any application.

 

[ivlsi]

So, how a simple SyncFIFO might be connected to AHB signals?

How to connect FIFO FULL and FIFO EMPTY to AHB signals?

What's behavior of the AHB Master when Slave asserts HRESP to HIGH (signalling ERROR)?

 

[sharath666]

You can connect a combination of HWRITE and HREADY to the write enable. You can map the write data directly. There is no way to connect the full and the empty. In case of error, either the master can abort or reinitiate the transaction.

 

[ivlsi]

In case of error, either the master can abort or re-initiate the transaction

So, probable FULL and EMPTY signals of FIFO might be connected to HRESP, which purpose is ERROR indication? Why not?

It's hard to believe that a regular FIFO cannot be used as Slave on AHB.

 

[sharath666]

AHB is not meant for interfacing to a FIFO. Only 2 parties can talk over AHB. One is an AHB master and the other is an AHB slave. I don't know how is HRESP related to FULL/EMPTY.

 

[D.A.(Tony)Stewart]

There may be wait states for each transaction, so check with supplier specs

e.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439d/CACDHCFH.html

 

[ivlsi]

I don't know how is HRESP related to FULL/EMPTY

The FIFO FULL and READY are OR'ed and gated respectively with HWRITE in such way so a Write Access to the FULL FIFO will rise HRESP indicating ERROR (the similar for FIFO EMPTY).

Will it work? Do you see any issues?