I am really grateful to you for this wonderful interaction,I really appreciate your help
module top (in, clk, reset, enb, out);
input [7:0] in;
input clk;
input reset, enb;
reg [7:0] a; // the mapper should place this into the input IOBs
output reg [7:0] out; // the mapper should place this into the output IOBs
always @ (posedge clk)
begin
if (reset)
a <= 8'b0;
else if (enb)
a <= in;
else
a <= a;
out <= a;
end
endmodule
Section 6 - IOB Properties
--------------------------
+-------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+-------------------------------------------------------------------------------------------+
| clk | IOB | INPUT | LVCMOS25 | | | | | |
| enb | IOB | INPUT | LVCMOS25 | | | | | |
| in<0> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<1> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<2> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<3> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<4> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<5> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<6> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| in<7> | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD |
| out<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| out<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | |
| reset | IOB | INPUT | LVCMOS25 | | | | | |
+-------------------------------------------------------------------------------------------+
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