Advice on placing a snubber circuit as close as possible to the MOSFET

[mike buba]

Hi All,

I am trying to place an RC snubber circuit across MOSFETs in my project and having trouble finding the optimal component placement. The basic schematics is below.

For the MOSFET, I am using the TO-247-4 package (C3M0075120K1). At this stage I do not know the required R_snubber and C_snubber values, so to have the option of tuning, for R_snubber I have selected the TO-220 package (20 W power rating, 2 kV, Bourns PWR220T-20 can go from 100 mOhm to kOhm in values), and for C_snubber BFC237524121 for now with lead spacing 10 mm and additional 15 mm pad for higher capacitance.

The general advice on placing is "placing the snubber capacitor as close as possible to the MOSFET minimize the stray inductance of the circuit".

However, I am having trouble implementing this. I have tried many versions and would appreciate a bit of help. This is what I have. The MOSFET will go in the heatsink, so I cannot put anything below. Snubber capacitor and resistor are as close as possible.

Any other options to make them even closer?

I am also not sure how to 'exit' with the drain and source high voltage/current signals. As if the snubber circuit is in the way. Or this should be okay? I just have to add board cutouts to get some creepage for the high voltage circuit.

Thanks, MB

 

[cupoftea]

The thing is there is not a massive need for snubber where you show...because those FETs are diode clamped to the rails, and so they will not get overvoltaged.
If you are doing a half bridge SMPS or LLC, then i would say do not put a snubber there at all. Unless maybe just a little RC just to kind of slightly blunt the edges of the dVds/dt waveform.

 

[mtwieg]

I have selected the TO-220 package (20 W power rating, 2 kV, Bourns PWR220T-20 can go from 100 mOhm to kOhm in values), and for C_snubber BFC237524121 for now with lead spacing 10 mm and additional 15 mm pad for higher capacitance.

Are you sure you need such large snubber components? Snubber capacitance is typically three times Coss, so we're talking hundreds of pF at most. You can get high voltage C0G/NP0 MLCCs which are far smaller and cheaper than that film cap, for example https://www.digikey.com/en/products/detail/yageo/CC1206JKNPODBN221/5884418

As for the resistor, power is roughly P=fsw * Cs * V^2, where Cs is the snubber capacitance. Depending on your bus voltage and fsw, each snubber may only need to dissipate a couple watts, in which case you can just use SMT components, making layout far easier

The general advice on placing is "placing the snubber capacitor as close as possible to the MOSFET minimize the stray inductance of the circuit".

More specifically, the parasitic inductance of the snubber should be much lower than the parasitic inductance of the bridge circuit being snubbed.

You should first prioritize reducing the parasitic inductance of the bridge circuit itself. Usually this is a matter of putting small DC bus capacitors (far larger than the RC snubbers) nearby each bridge, with proper planes for GND and bus. I can't see any such capacitors in your layout though.

 

[cupoftea]

you should first prioritize reducing the parasitic inductance of the bridge circuit itself. Usually this is a matter of putting small DC bus capacitors (far larger than the RC snubbers) nearby each bridge, with proper planes for GND and bus. I can't see any such capacitors in your layout though.

Well said this...i chide myself for not seeing this point before i gave my own.

 

[Easy peasy]

Local bus caps are indeed important for turn off - the more the merrier - even 100nF here and there - but mainly what fits well

for heatsinking the snubber R's you have to use imagination - extensions to the heatsink bar, and sometimes wires from the R to the
C to the pcb

also the R should always be on the noisy side - i.e. connected to the totem pole centre

If you turn on slowly - you may need zero snubbing - turning off fast is handled by the local smaller bus caps.

 

[mike buba]

Thank you all for the replies and valuable advice.
This is the schematic for the T-type single leg.

The calculation for R_snubber is as follows:
P_snubber = C_snubber × f_sw × V²
where:
• f_sw is switching frequency and
• V is the voltage that the capacitor charges to on each switching transition.
= 220 pF × 20 kHz × 680^2 = 2.034 W

Hence, I have decided to use two 2W resistors in parallel.

Snubber resistance required for optimal damping is calculated as:
R_snubber = 1 / (4 × π × f_r × C_snubber),
where:
• f_r is the ringing frequency.

But at this stage I do not know f_r, so for R_snubber I have selected two 4.7Ω in parallel (MCPAS122WJ047JT4E, 2W, Max. Working Voltage 500 V), with other available resistances of MCPAS122W...: 1Ω, 4.7Ω, 6.8Ω, 10Ω, ... so few options there.

By the way, not many resistors in that range have that high working voltage, hence size 2512.


I have also started work on the layout:

 

[Easy peasy]

Just a note that the snubbers across the supply rails will do almost zero ( they don't see much in the way of dV )

putting caps across the gate drive with long traces to the fet ( and the drive ) will cause VHF ringing on the gate drive - so don't do this unless you have a very specific reason - and know exactly what you are trying to achieve.

--- Updated Mar 3, 2025 ---

also the R's across G-S would be better at 5k6 ( ~ 3mA @ 18V )

 

[FvM]

The art of making of inverters with little overshoot and EMI is mainly based on making low inductance switching branches. Your latest PCB sketches give no idea of overall switcher layout, they are useless to decide about possible snubber necessity. As stated by others, you don't need it in a well designed bridge or three-level inverter.

Similarly, to choose gate circuit components, you must look at the whole picture, driver, series resistors, connection traces and wires, gate capacitance. Latest PCB sketches have much too small (= too inductive) gate traces for sure.

 

[KlausST]

Hi,

the phrase: "placing a snubber circuit as close as possible to"

.. indeed means: the snubber circuit loop needs to have low (stray) inductance.
usually done by:
* suitable PCB layout, like using a really solid GND plane
* using suitable electronic devices, like NOT using wirewound resistors.

Klaus

 

[mike buba]

Hi all, I have created full schematics, and after several iterations, the PCB layout I am happy with.
Can you please review, comment and suggest improvements? It is a T-type four-leg topology. Vdc = 700, Vac = 400 Vrms, 50 Hz, total power: 5 kW.

Schematics:
View attachment T_Type_Inverter_v4_006.png View attachment T_Type_Inverter_v4_001.png View attachment T_Type_Inverter_v4_005.png

Layout: top (DC+ and PWM signal), middle 1 (GND (power and DGND)), middle 2 (+5 V and Phase Out), bottom (+15 V and DC-)
View attachment T_Type_Inverter_v4_007.png View attachment T_Type_Inverter_v4_008.png View attachment T_Type_Inverter_v4_009.png View attachment T_Type_Inverter_v4_010.png

--- Updated Mar 24, 2025 ---

PCB 3D models:

Gate driver schematic is here: https://www.edaboard.com/threads/sic-mosfet-gate-driver-design-and-functionality.412033/post-1781106