Advice on CPU Physical Designing

[tito_ee]

Hi,
I have been asked to handle the physical layout for a 64 bit RISC-V CPU core. The target frequency is 2GHz at slow corner in 7nm.The priority order is Performance > Power > Area. So I needed some advice how to layout the clock tree structure efficiently to hit this frequency . Since its a CPU the only macros present in the design are SRAMs (around 100 in count ). Advices other than clock tree like Power structure designing, Standard cells to be used ( already using MultiBit flops and Low Voltage threshold cells), CLock Gating optimisations etc. which will help to meet the target will be helpful as well

 

[ThisIsNotSam]

clock tree is only one element of a very complicated equation.
start with logic synthesis, zero wireload. see if you can reach 2GHz. then see how far you can push further. if you get to 2.2GHz, 2.15GHz, there is hope.
in general, placement and routing will deteriorate your timing. with rare exceptions for things like useful skew.
for standard cells, give the tools many libraries to choose from.
for power grid, performance will be impacted only if you do a very lousy job such that placement is compromised. otherwise it is a reliability problem, not a performance problem.

overall, what you need to apply are engineering skills. and that you have to pick up by yourself.

 

[navpics1]

In synthesis : push for 7-8% more freq than desired. Use physical synthesis / physical aware atleast.
Take care of multi input cells with low drive strength (typ AOI/OAI regular culprit's)

PNR :
Floorplan & placement : if possible refer to core implementation reference flow. This gives fairly good idea, watch out of critical path groups , magnet module placement , Io critical modules , data-flow diagram. ALU/MAC placement is critical.
Do an trial detail routes here itself , just as a test for Ur channel congestion across macros

CTS : clk mesh or MSCTS (still difficult) for 2 GHZ
Look for CTS exceptions , spend time to analyze bad skew , bad WNS clk groups

Post-cts : watchout for hold hotspots, identify them during first runs and padding in subsequent runs
If QOR setup doesn't meet Ur req , there is no point in moving further, go back to placement

Route & post route : EDA can take care , only issue is runtime.

Postroute hold fixing done by regular PNR tools are not optimal. Go to PT and chk