The main point to remember is to write code that another engineer will understand. Comments should be about "why" you're doing something - the "how" should be reasonably obvious from the code.
The overly-creative code is IMO some of the worst coding I've run across, namely because nobody bothers to explain why or what they are trying to do, which usually involves taking advantage of some tool or language quirk. If you do something like that then document it with detailed comments about how this works with XYZ tool and what is the expected result.Otherwise, don't write "overly-creative" code without comments. Retain whatever aesthetic style an existing file uses. etc...
If you want to write good structured code then read the following
https://gaisler.com/doc/vhdl2proc.pdf
use ieee.std_logic_arith.all;
cpu0 : cpu_sparc port map (rst, clk, ici, ico, dci, dco, fpui, fpuo);
fpu0 : fpu_core port map (clk, fpui, fpuo);
cache0 : cache port map (rst, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, crami, cramo);
cmem0 : cachemem port map (clk, crami, cramo);
I cant see a date for this paper.
IIRC, it was from 1999. The style that it was trying to replace was the style where every signal is in its own process. Some of the arguments make way more sense if you compare them against common standards from 20 years ago.
The article recommends the one-process state machine coding style, and I agree with it.
That is a good example of why one-process is dangerous. There is a comment "output is a function of the current state only". This is wrong -- there is an extra register stage. Is this an error? probably not. but there is a delay for no reason and the author doesn't seem to notice.
I agree that logic should be registered where possible and latches should be avoided. That is a different argument.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 process(clk, reset) begin if reset = '1' then current_state <= idle; op <= '0'; elsif rising_edge(clk) then case current_state is when idle => if start = '1' then op <= '1'; current_state <= led_on; end if; when led_on => if toggle = '1' then op <= '0'; current_state <= led_off; end if; when led_off => if toggle = '1' then op <= '1'; current_state <= led_on; end if; when others => op <= '0'; current_state <= idle; end case; end if; end process;
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