ADPLL using Verilog? Not working!

[sonaiko]

adpll

Guys I am trying to implement ADPLL in verilog using Quartus-II so I can synthesis my model to an FPGA.

**broken link removed**I have found this code that implements an ADPLL designed by R.E.Best on 1999. I tried to simulate this code to test it but it is not working. Compliation OK but no simulation results. Only CK toogles but all other signals are at zero state.

Please help me figure this out. If this code doesnt work out I think I wont try to write my own code for a different ADPLL!

Thank you.

module pll (u1, u2, fc, reset);

parameter M  = 5;			//5 3
parameter N  = 4;			//4 2
parameter NF = 0;			//0 1


input  u1, fc, reset;
output u2;
wire FF1_in, FF3_in, MF_in, Start, CK, reset, Reset;
wire [N:0] Modulus_Control;
reg u1_star, Ud, Load;
wire u2, div_out;
reg u2_prime;
reg [N:0] N_Uf;
reg [NF:0] feedback_divider;


//*****PULSE FORMING CIRCUIT******//
inverter nt3(FF1_in, u1);
always @(negedge u1 or negedge reset)
begin
 if(!reset) u1_star <= 0;
 else u1_star <= !u1_star;
end
assign CK = u1 && u1_star; 
assign MF_in = !u1_star; 
mf mf1(.out (Start), .in (MF_in) );
//*****END PULSE FORMING CIRCUIT****//

jk jk1(.Q (FF3_in), .J (Start), .K (u2_prime), .reset (reset), .fc (fc) );
//jk jk1(.Q (FF3_in), .J (Start), .K (u2) );


always@(u2)
u2_prime <= u2;
/*
always@(posedge u2 or negedge reset)
begin
 if(!reset) 
  begin
  u2_prime <= 0;
  feedback_divider <= 0;
  end
 else 
   begin
   feedback_divider <= feedback_divider + 1;
   if(&feedback_divider) u2_prime <= !u2_prime;
   else u2_prime <= u2_prime;
   end
end
*/

//*****DIGITALLY CONTROLLED OSCILLATOR****//
mcounter #(M) mc1(.u2 (u2), .div_out (div_out), .Reset (Reset), .reset (reset) );
ndivider #(N) nd1(.div_out (div_out), .Load (Load), .fc (fc), .Modulus_Control (Modulus_Control), .reset (reset) );

always @(posedge fc)
Load = div_out || Start;

assign Reset = Start;
//*****END DCO*****//


//***PHASE DETECTOR*****//
always@(posedge u1_star or negedge reset)
begin
	if(!reset) 	Ud <= 0;
        else 		Ud <= FF3_in;
end
//***END PHASE DETECTOR***//

//***LOOP FILTER***//
always@(posedge CK or negedge reset)
begin
 if(!reset) 	 N_Uf <= 6'b010000;
 else if(Ud==0)  N_Uf <= N_Uf+1;
 else 		 N_Uf <= N_Uf-1;
end

assign Modulus_Control = N_Uf;

//***END LOOP FILTER***//

endmodule




///////////////////////


module mcounter(u2, div_out, Reset, reset);
parameter M = 2;

input div_out, Reset, reset;
output u2;
reg [M:0] value;
reg u2;

always@(posedge Reset or posedge div_out or negedge reset)
begin
 if(!reset) 
  begin
  value <= 0;
  u2 <= 0;
  end
 else if(Reset)
  begin
  value <= 0;
  u2 <= 0;
  end
 else 
   begin
   value <= value + 1;
   //if (value==5'b11111) u2 <= !u2;
   if (&value==1) u2 <= !u2;
   else u2 <= u2;
   end
end
endmodule




module ndivider(div_out, Load, fc, Modulus_Control, reset);
parameter N = 2;

input Load, fc, reset;
input [N:0] Modulus_Control;
reg [N:0] value;
reg div_out_pre;
output div_out;

//always@(posedge Load or posedge fc or negedge reset)
always@(posedge fc or negedge reset)
begin
if(!reset) 
  begin
  value <= 0;
  div_out_pre <= 0;
  end
else if(Load) 
  begin 
  value <= Modulus_Control;
  div_out_pre <= 0;
  end
else if(value != 0) 
  begin
  value <= value - 1; 
  div_out_pre <= 0;
  end
else div_out_pre <= 1;
end

assign div_out = div_out_pre;

endmodule

module jk (Q, J, K, reset, fc);
input J, K, reset, fc;
output Q;
reg Q;
reg Q1, Q2;


always@(posedge J or negedge reset)
begin
	if (!reset)	Q1 <= 0;
	else if(K==1)	Q1 <= !Q;
	else		Q1 <= 1;
end
always@(posedge K or negedge reset)
begin
	if (!reset)	Q2 <= 0;
	else if(J==1)	Q2 <= !Q;
	else		Q2 <= 0;
end

always@(Q1 or Q2)
begin
Q <= Q1 || Q2;
end
/*
always@(posedge J or posedge K)
begin
	if((J==0)&&(K==0)) 		Q <=  Q;
	else if((J==0)&&(K==1))		Q <=  0;
	else if((J==1)&&(K==0))		Q <=  1;
	else 				Q <= !Q;
end
*/	

endmodule

module mf (out, in);
input in;
output out;
wire flag, flag2;
reg out;

inverter nt4 (flag, in);
inverter nt5 (flag2, flag);

always@(in or flag2)
begin
  if(!in) out <= 0;
  else out <= in ^ flag2;
end

endmodule

module inverter (out, in);	// inverter

output out;
input in;
reg out;

always @(in)
begin
#1 out <= !in;
//out <= !in;
end

endmodule

 

[indoprojectconsultancy]

adpll verilog

u need to contact indoprojectconsultancy@ymail.com.We have developed a running code for ADPLL in VERILOG which is synthesizable in XILINX ISE

 

[FvM]

adpll verilog code

The mf module (mf apparently means monoflop) cant't work this way. Pulse forming by a logic cell delay line as intended here is basically possible, but with modern synthesis tools, keep attributes are required to prevent the compiler from removing the delay chain during logic synthesis. Also two logic cells are possibly a too small delay for an asnychronous edge detector.

By applying similar corrections, I expect that the example can be synthesized with &#65ltera Qu&#97rtus or other tools.