ADPLL Output lock condition

[pmuppala]

Hi,

I am doing an adpll in 90nm technology. I am not able to understand how to lock the DCO divider output to REF frequency. DCO divider output is oscillating up and down around the target frequency but not locking to it. Please do post if you think i have missed something.

Thanks,
Muppala.

 

[ebuddy]

The feedback clock from DCO divider and REF clock are phase locked when in lock situation - so the FB clock edges are moving back and forth around REF clock edges. This is the what PLL is suppose to behave. You can either look at the PFD/integrator output or look at the FB clock frequency in certain time window to declare if the lock situation has been achieved.

 

[pmuppala]

ebuddy thanks for replying so fast. I looked at the FB clock frequency and the frequency is oscillating around the target clock. For example if my target is 125 MHz, the FB clock frequnecy is oscillating around 120 MHz to 130MHz but not quite locking. My DCO has a frequency resolution of 0.6 MHz. Hence i would generally want the output to lock at 124 or 126 Mhz if not 125 Mhz exactly. But i couldnt understand why the FB freq is oscillating from 120Mhz to 130Mhz.

---------- Post added at 17:36 ---------- Previous post was at 17:22 ----------

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In the image attached u can see that the blue line is the REF frequency and the RED line is the FB frequency. The FB freq is oscillating around the target as shown shown.

---------- Post added at 17:38 ---------- Previous post was at 17:36 ----------

https://obrazki.elektroda.pl/47_1295908522.png

 

[ebuddy]

Looks like your PLL loop bandwidth is way too low. You probably want to check out the path from your PFD output to DCO input. Usually there is a charge pump and a loop filter in analog PLL or digital equivalent implementations in DPLL there. Probably a delay somewhere is excessive, or there is a flaw in your DCO design.