addition of IEEE754 single precision floating point.......

[watabe112]

can anyone help me.....how to add IEEE754 floating point.....i need to find the mean....firstly,i need to add...then divide....i need to write it in verilog.....can anyone help me....:|

 

[vipinlal]

There are two or three floating point adder codes in opencores. Download them and check the codes. It will give you an idea about the coding.

 

[TrickyDicky]

Altera has a full list of floating point IP cores. Find them in the mega-wizard in quartus.

 

[watabe112]

hi everyone......can anyone check for me.....whether my program is right?.....i need to add IEEE754 single precision number.......

...............................................code..............................................................................

module modadd(
input clk,
input [31:0] a,
input [31:0] b,
output reg [31:0] r
);

wire sa;
wire [7:0] ea;
wire [22:0] fa;
assign sa = a[31];
assign ea = a[30:23];
assign fa = a[22:0];

wire sb;
wire [7:0] eb;
wire [22:0] fb;
assign sb = b[31];
assign eb = b[30:23];
assign fb = b[22:0];

/* Stage 1.
* Sort the numbers according to the exponent.
* A becomes the number with the biggest exponent.
* Negate b in case of substraction.
*/

reg sa1;
reg [7:0] eL;
reg [22:0] fracL;
reg sb1;
reg [7:0] eS;
reg [22:0] fracS;

always @(posedge clk) begin
if(ea > eb) begin
sa1 <= sa;
eL <= ea;
fracL <= fa;
sb1 <= sb;
eS <= eb;
fracS <= fb;
end else begin
sa1 <= sa;
eL <= eb;
fracL <= fb;
sb1 <= sb;
eS <= ea;
fracS <= fa;
end
end

/* Stage 2
* Add leading (integer) bits on the mantissas.
* Compute the difference between the exponents.
*/

reg [7:0] diff;
reg sa2;
reg [7:0] ea2;
reg [23:0] fa2;
reg sb2;
reg [23:0] fb2;
reg [7:0] eb2;
always @(posedge clk) begin
diff <= eL - eS;

sa2 <= sa1;
sb2 <= sb1;
eb2 <= eL;
fb2 <= fracS;

end

/*stage 3*/

reg [22:0] fr;
reg [22:0] fracr;
reg [7:0] er;
reg sr;

always @(posedge clk) begin

fr <= {(1+fracS)};
fracr <= fr>>diff;
er <= eb2;
sr <= sb2;
end


always @(*)
begin
r[31] = sr;
r[30:23] = er;
r[22:0] = fracr;
end

endmodule

......................................................................end...........................................................

it seems that the output is not the same as my calculation........

 

[vipinlal]

Do a manual calculation and find out which intermediate output is failing. For example check whether the intermediate output after stage1 or stage2 or stage3 is wrong..

where do you actually add the fract parts of the numbers? I dont see that in the code.

 

[watabe112]

sorry....i forgot that part.....can u tell me....how to represent 1.100000 in verilog code.....can u give me an example......

 

[vipinlal]

reg [7:0] value;
value = 1100000;

this should work. Just keep in mind the decimal position. I am not that good with Verilog, so I cant give you an exact code snippet.

 

[watabe112]

can u give me an example on how to coding for 1.010101...........how to add the leading bit(1.) in the verilog.......