chillimillii
Newbie level 5
arrays in vhdl
Hi all!
I have to add two 3 x 1 integer arrays in VHDL . I have written the following piece of code ...it gets synthesized but it fails in implement design . I don't know whats the problem with it . can anyione help me with it ....
architecture Behavioral of TEST is
type int_array is array(0 to 3, 0 to 0) of integer range 0 to 7;
signal w,t,u: int_array ;
begin
g1:for i in 0 to 3 generate
h1: for j in 0 to 0 generate
w(i,j) <= t(i,j) + u(i,j);
end generate h1;
end generate g1;
end Behavioral;
Hi all!
I have to add two 3 x 1 integer arrays in VHDL . I have written the following piece of code ...it gets synthesized but it fails in implement design . I don't know whats the problem with it . can anyione help me with it ....
architecture Behavioral of TEST is
type int_array is array(0 to 3, 0 to 0) of integer range 0 to 7;
signal w,t,u: int_array ;
begin
g1:for i in 0 to 3 generate
h1: for j in 0 to 0 generate
w(i,j) <= t(i,j) + u(i,j);
end generate h1;
end generate g1;
end Behavioral;