adding flops ( pipelining) to meet timing in backend

jaya sree said:

hai ,

generally if data delay is much more than clock period , that path is declared as multi cycle path .Then why to do break that path ( do pipelining ) and add flops to meet timing.Please explain in detail.

thank you
jaya sree

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jaya sree said:

hai ,

generally if data delay is much more than clock period , that path is declared as multi cycle path .Then why to do break that path ( do pipelining ) and add flops to meet timing.Please explain in detail.

thank you
jaya sree

Click to expand...

jeevan.life said:

Jaya, What is the value addition with this approach? Any way you will have the same path with an additional flop resulting in added area and power. No advantage in timing view point.

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dll_fpga said:

Suppose your combo logic takes 10 ns to complete an operation and lets assume the clock to be of timeperiod 5ns .In this scenario we have to break the combo logic into 2 halves lets say each takes 5 ns.In the first 5 nano second one part of the combologic is completed ,so we will register to a flop and in the next 5 ns second half of the combo logic completes and we will register this .After this process we will combine the outputs of the 2 flops which act as the actual output of the combo block.

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