adding a core from coregenerator to XPS

[guduru]

Hi,
iam working on xilinx platform studio.when i try to add "DCT" from coregenerator as user logic to the OPB bus of power PC processor im getting following error.

ERROR: "logical block 'dct with type 'dctd' could
not be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol 'dctadd' is not
supported in target 'virtexIIpro'."
i synthesized the code in Xilinx 8.2 and generated the netlist successfully but
when i tried to update bitstream after importing my DCT core into the project I got this error .
anybody please help me in solving this problem?
Thanks in advance....

 

[shawndaking]

i guess you created a xps pcore using this dct core.

the error is translate error means the ediff code of the dct is not found or exist.

if you generated ipcore for the dct then the edn or ngc should probably be located in the netlist sub-folder, hdl style should be MIX, and there should be a bbd file under data sub-folder.