ADC simulation testing using Verilog model for a block

[nijMcnij]

ADC simulation testing

hello all,

i am designing an ADC, and i was told that there is a way to create a verilog model for a block which can be connected to the ADC digital outputs.

the verilog block can then write the digital codes from the ADC to a file.

how can i do this

many thanks

 

[willyboy19]

Re: ADC simulation testing

Try use $fstrobe function and it will do the job.

 

[swicap]

ADC simulation testing

VerilogA model can do that,
it is easy to write this va block, check veriloga reference.

 

[nijMcnij]

Re: ADC simulation testing

i have created a verilog A model that uses the $fstrobe function.

hwoever the outputs of the ADC are 3.3V for a digital 1 and 0 for a digital 0....how can i use $fstrobe inorder to save a 1 for every 3.3V on the digital outputs.

many thanks

 

[swicap]

ADC simulation testing

$fstrobe can export data to a file.
use matlab to analysize the data.
It will be very easy to solve the problem u met.

 

[redswat]

ADC simulation testing

maybe you can use a ideal DAC in analog netlist to test your ADC outputs

 

[chenliy]

Re: ADC simulation testing

You could connect the input of DAC with the output of ADC.