Continue to Site

# ADC simulation testing using Verilog model for a block

Status
Not open for further replies.

#### nijMcnij

##### Full Member level 1

hello all,

i am designing an ADC, and i was told that there is a way to create a verilog model for a block which can be connected to the ADC digital outputs.

the verilog block can then write the digital codes from the ADC to a file.

how can i do this

many thanks

#### willyboy19

hwoever the outputs of the ADC are 3.3V for a digital 1 and 0 for a digital 0....how can i use $fstrobe inorder to save a 1 for every 3.3V on the digital outputs. many thanks #### swicap ##### Member level 5 ADC simulation testing$fstrobe can export data to a file.
use matlab to analysize the data.
It will be very easy to solve the problem u met.

### nijMcnij

Points: 2

#### redswat

##### Newbie level 6

maybe you can use a ideal DAC in analog netlist to test your ADC outputs

#### chenliy

##### Junior Member level 2

You could connect the input of DAC with the output of ADC.

Status
Not open for further replies.