sethtalk
Member level 3
aaron buchwald successive approximation
[ADC Seminar]-Buchwald, Ph.D,-Nov,2006
ADC Seminar,Nov,2006
Speaker:Aaron Buchwald, Ph.D., Mobius Semiconductor Co,Ltd
date: Nov,2006
title:Challenges and Solutions for A/D Converter Design in Deep Submicron CMOS
Abstract─Low-power, high-performance A/D conversion has evolved
as a key requirement in many modern communication syst
-ems. This short course covers topics relevant to the
design of power- and performance-optimized ADCs in modern
CMOS technology.
The first part of this presentation discusses a systematic
methodology for the design of transconductance amplifiers
with short channel devices. Using Spice-generated look-up
tables that capture the tradeoff between speed (gm/Cgg)
and power efficiency (gm/ID), the proposed approach removes
the need for mathematically complex device equations. As a
result, amplifiers can be designed for an optimum tradeoff
between speed, noise and power dissipation without iterative
Spice level simulations and "tweaking".
Followed by a discussion on power dissipation limits in
today’s ADCs, the second part of this seminar focuses on a
new class of ultra-low power "digitally assisted" ADCs. These
converters are based on minimalistic, but power efficient
analog sub-circuits and use digital processing for performance
recovery and/or enhancement. Preliminary results indicate that
this approach may deliver order-of-magnitude improvements in
power efficiency.
Outline Outline
-DAY-1 Flash & Folding ADCs
-Overview of ADCs
-Basic Principles
-Simple Design Examples (Flash)
-Circuit building blocks
-Comparators
-Preamps
-Averaging
-Circuit Implementation
-Design Example Folding & Averaging ADCs
-Averaging
-Folding
-Specifying and Testing ADCs
-DAY-2 Multi-step and Pipelined ADCs
-Multi-step and Subranging ADC Overview
-Design Example Successive Approximation
-Fundamentals of Pipelined ADCs
-Pipelined: Design Example
-Circuit Building blocks
-Calibration Techniques: Survey of techniques
[ADC Seminar]-Buchwald, Ph.D,-Nov,2006
ADC Seminar,Nov,2006
Speaker:Aaron Buchwald, Ph.D., Mobius Semiconductor Co,Ltd
date: Nov,2006
title:Challenges and Solutions for A/D Converter Design in Deep Submicron CMOS
Abstract─Low-power, high-performance A/D conversion has evolved
as a key requirement in many modern communication syst
-ems. This short course covers topics relevant to the
design of power- and performance-optimized ADCs in modern
CMOS technology.
The first part of this presentation discusses a systematic
methodology for the design of transconductance amplifiers
with short channel devices. Using Spice-generated look-up
tables that capture the tradeoff between speed (gm/Cgg)
and power efficiency (gm/ID), the proposed approach removes
the need for mathematically complex device equations. As a
result, amplifiers can be designed for an optimum tradeoff
between speed, noise and power dissipation without iterative
Spice level simulations and "tweaking".
Followed by a discussion on power dissipation limits in
today’s ADCs, the second part of this seminar focuses on a
new class of ultra-low power "digitally assisted" ADCs. These
converters are based on minimalistic, but power efficient
analog sub-circuits and use digital processing for performance
recovery and/or enhancement. Preliminary results indicate that
this approach may deliver order-of-magnitude improvements in
power efficiency.
Outline Outline
-DAY-1 Flash & Folding ADCs
-Overview of ADCs
-Basic Principles
-Simple Design Examples (Flash)
-Circuit building blocks
-Comparators
-Preamps
-Averaging
-Circuit Implementation
-Design Example Folding & Averaging ADCs
-Averaging
-Folding
-Specifying and Testing ADCs
-DAY-2 Multi-step and Pipelined ADCs
-Multi-step and Subranging ADC Overview
-Design Example Successive Approximation
-Fundamentals of Pipelined ADCs
-Pipelined: Design Example
-Circuit Building blocks
-Calibration Techniques: Survey of techniques