ADC sampling rate questions

[Vlad.]

Hi,

I have some questions regarding a DaQ system based made by me with FPGA and MAX1285 (12 bit SPI interface):

1. It the sampling rate dependent with the SPI SCLK ?I think yes, in datasheet is max SPI CLK is 4.8 MHz and the max sampling rate is 300 ksps, but I don't see a relation between them.
2. For DC voltages readings is required such a huge sampling rate? Or maybe there is a limit, also the voltages which are read are not really constant from amplitude point of view.

I am sorry if was posted in other topic.

Regards,
Vlad

 

[KlausST]

Hi,

1) sampling rate is NOT depending on SPI SCLK. It is just controlled by the CS.

datasheet clearely says:
"A CS falling edge initiates a conversion sequence:"

2) You may pull CS low every 4us or you may pull it low every minute... this starts a conversion every 4us or every 1 minute.

...

Or maybe there is a limit, also the voltages which are read are not really constant from amplitude point of view.

if voltage changes with time, then ther is AC. The faster it changes the higher is the frequency.
So first you have to decide what frequency this is. We can not know this.
(or you have to limit this frequency by the use of a low pass filter)

Then - according nyquist theorem - you need to sample with more than twice the highest included signal frequency.

Klaus

 

[crutschow]

..................
2. For DC voltages readings is required such a huge sampling rate? Or maybe there is a limit, also the voltages which are read are not really constant from amplitude point of view.
.................

For true DC you only need 1 sample.
In practice you likely want to sample at a higher rate, depending upon how often you want to know if there is a change in the DC voltage.
If here is any noise on the DC you may want to digitally average several samples to filter the noise.

 

[dick_freebird]

Multiple samples can get you enhanced accuracy but your
rate for DC can be pretty low, set by things like your test
time budget, part self-heating under bias / load, etc.

SPI clock needs to be able to haul out all of the bits
in one acquisition cycle period (or less) otherwise the
data may be corrupted (write output register while
read is still going on. 4.8MHz looks a lot like
300kHz*16 bits. Although you say it's 12 bits maybe
the packet is 16, either arbitrarily (from the controller)
or for some cause like start/stop/parity/8b10b bit
overhead.

 

[asdf44]

If your'e truly reading DC you may want to shop around for a lower sampling rate but higher number of bits.

Although 12-bit/300k is right in the sweet spot in terms of ADC price and availability so you're not going save much money going any direction from there.

As others have said, if the sampling rate is higher than you need you can put it to use by averaging. An RC filter equivalent is easy to implement in an FPGA.

 

[KlausST]

Hi,

Averaging may not improve accuracy. Accuracy is specified with offset error, gain error and DNL.
Averaging may improve precision because of reduced noise. Only if analog_noise + ADC_input_noise is larger than 1 LSB.
Averaging will improve resolution. If analog_noise + ADC_input_noise is larger than 1 LSB.
(Noise...including ripple voltage over the time of averaging)

*****
Often noise is what you want to avoid. Experienced electronics engineers may (easily) keep nois below a 16 bit ADC LSB.
But in the cases above one needs at least the LSB to toggle. Averaging a stable ADC output will give no improvements in precision nor in resolution. Therefore in some cases where averaging is used one adds a dither signal to the analog input to ensure the LSB(s) to toggle.
But this problem only occurs when the input signal is DC or only very slow moving. And low resolution ADCs and low analog noise level.
DC input signal and low resolution ADC is given by the OP.
*****

If you really need higher resolution than 12 bits, then use a higher resolution ADC.

Klaus

 

[Vlad.]

Hi all,

Thank you very much for your answers. I want to monitor some parameters like voltage references and currents, which are DC voltages. The purpose is to find if some fast transient variations may be occur, this is why I choose a large sampling rate ADC.
I don’t think I need a resolution higher than 12 bits, because with this ADC (ranges from 0 to 2.5V) I will have 600uV resolution.
Yes I can do a processing, like averaging in FPGA, but I am afraid that I will loose the good data, e.g transient variations, if I will do a mean of the values.

Regarding the ADC conversion: So what do you mean when ADC has finished a conversion, it mean that ADC taked a sample and converted it to digital code? in my case for 300KSPS mean 300 k conversions?

Thank you,
Vlad

 

[KlausST]

Hi,

now we have a different situation. I (wronly) thought you were interested in DC values.

But now you say you are interested in transient variations (maybe as a second result of the measurement). This for sure calls for high frequency sampling.
Again you need to take care about nyquist. The transients include high frequency components. You need to capture them. You need to decide what dV/dt they might have, what´s the transient peak-to-peak voltage is and how long a transient lasts. And how precise you want to detect them.

Maybe you can upload a scope picture of the transients. With timing and voltage information.

Klaus

 

[Vlad.]

Hi,

Yes, I don't have a scope picture, because these variations are unknown, and are the result of the future behavior of some device in hard working conditions. but I suppose will be some transients by the factor of tens of us.
So, I have to get through it. I have about 30 pieces of MAX1285, and this ADC its fits well on my application.

What about the last question on previous post?

Thanks,
Vlad

 

[KlausST]

Hi,

Regarding the ADC conversion: So what do you mean when ADC has finished a conversion, it mean that ADC taked a sample and converted it to digital code? in my case for 300KSPS mean 300 k conversions?

300ksps means 300000 conversions per second. 3.33us from conversion to conversion.

Klaus

 

[FvM]

Although you say it's 12 bits maybe the packet is 16, either arbitrarily (from the controller) or for some cause like start/stop/parity/8b10b bit overhead.

Simple reason, SPI frame length is a multiple of 8 bits by protocol specification.

 

[Vlad.]

@KlausST

Thank you, so in fact the sampling rate is controlled by me (e.g FPGA), by the number of conversions per sec requested by FPGA? I assume an conversion is when is pulled CS low, and I read all the data and after I put CS high, and go over again.