Zedman
Full Member level 6
I am trying to use ADC0831 A/D chip, I know this is simple, but i stuck with it. Datasheet says: Conversion Time is 32µs, so it can do ~30000 samples per second and I tought I can sample a 15kHz sine wave.
But it's not really works.
I created a basic config: Vref, V- is on GND, V+ tied to Vcc. So i have to get nearly 0xFF on the output.
But I only get 0x5A.
I've done a lot of timing change and I figured out that if I increase the clock high time than the amplitude increases too. To get full 255 bit resolution I have to do: clock UP / wait ~250 µs / clock DOWN. If i do i can get 0xFE. But it's far slower than I expected, and ds said.
What am i doing wrong?
I've seached in google, and found lot of examples using PIC / assembly, and they
are wait only a nop time @ 4MHz (iam running on 40 MHz so i waited at least 10 nops) between clock up/down.
I attached the timing diagram from the ds. (tset-up=250ns, tc=8 1/clock speed, max. clock speed is 400 kHz, so tc=~20-40µs)
It shows that if i running clock speed at 400.000Hz (clock high time: 2.5us) than the conversion time is 8 * (1/400.000)=20us.
But tc is from the falling edge of the first (dummy) clock pulse to the the falling edge of the 9th clock pulse. Maybe A/D conversion still running while I can shift out the incomplete result?
please lead me out from the trees...
But it's not really works.
I created a basic config: Vref, V- is on GND, V+ tied to Vcc. So i have to get nearly 0xFF on the output.
But I only get 0x5A.
I've done a lot of timing change and I figured out that if I increase the clock high time than the amplitude increases too. To get full 255 bit resolution I have to do: clock UP / wait ~250 µs / clock DOWN. If i do i can get 0xFE. But it's far slower than I expected, and ds said.
What am i doing wrong?
I've seached in google, and found lot of examples using PIC / assembly, and they
are wait only a nop time @ 4MHz (iam running on 40 MHz so i waited at least 10 nops) between clock up/down.
I attached the timing diagram from the ds. (tset-up=250ns, tc=8 1/clock speed, max. clock speed is 400 kHz, so tc=~20-40µs)
It shows that if i running clock speed at 400.000Hz (clock high time: 2.5us) than the conversion time is 8 * (1/400.000)=20us.
But tc is from the falling edge of the first (dummy) clock pulse to the the falling edge of the 9th clock pulse. Maybe A/D conversion still running while I can shift out the incomplete result?
please lead me out from the trees...