ADC input buffer

[the8thhabit]

hello
I am trying to design an input buffer for input driving of a SAR ADC.
Is it ok to use a huising amp which is a rail to rail amp?
Please help me what circuit is usually used.

 

[danadakk]

What is a "huising" amp ? Post a link to it.

Part number of SAR ?

Why the need for a buffer ? And electrical spec goals the buffer
is being considered ?

 

[the8thhabit]

What is a "huising" amp ? Post a link to it.

Oh, I made a mistake.
It is "huijsing amp"!

 

[theguardian2001]

I am trying to design an input buffer for input driving of a SAR ADC.
Is it ok to use a huising amp which is a rail to rail amp?

Hi. I am currently doing almost the same project, ie building a SAR ADC, and I will let myself share some thoughts regarding your question.

First of all, let me agree with danadakk that it is not entirely clear what do you mean by "input driving SAR ADC". The one I am starting to think is a buffer or an opamp used in your sample-and-hold circuit, since you can not apply a continuous waveform together with a discrete-time signal generated by a SAR register and a DAC to comparator's inputs. If that is the question then it will definitely depend on the S/H architecture that you are using - some of them may relax the specs.

If the question was regarding whether the mentioned opamp can be used as a buffer - yes, it can. I think that that is a good choice in terms of lowered output impedance, if we are considering the topology in general.

If I were you I would have started with designing an opamp in terms of maximizing its' GBW. The larger GBW - more stable the opmap in the follower-configuration. Even if the designed opamp appears to be unsuitable in your applications, you will easily identify what you are missing - gain, unity gain freq, settling time etc, and after that find a topology or a solution that helps to improve the parameters you need. It is relatively easy to re-build an opamp when you know technology limitations with "canonical" topologies.

 

[dick_freebird]

SAR ADC input would be a S/H or T/H amp and comparator kickback error its only challenge. Clocked comparators kick back hard, a SAR.ADC might have a plain old continuous time comparator with little Cin and no clock noise until after the compare has been made.

So get back to "what do you need and why?".

 

[the8thhabit]

I think I didn't make my question clear enough.
I knew Vin is used with a S/H switch.
I was wondering about the buffer for the SAR ADC to get a good sine signal coming into the input before it samples Vin using the s/h circuit.

1. I think I need to design a buffer with a large bandwidth for fast settling of Vin, and I was wondering if it is enough to set the BW of the buffer around 700MHz for sampling rate = 20MS/s, fbw (bandwidth of input sine signal ) = 10MS/s (for Nyquist ), with 10bit CDAC.

2. Also, I'm wondering why I need a clk to switch Vcm,ref, at buffer using a pmos source follower structure as shown in the second figure.

Hi. I am currently doing almost the same project, ie building a SAR ADC, and I will let myself share some thoughts regarding your question.

First of all, let me agree with danadakk that it is not entirely clear what do you mean by "input driving SAR ADC". The one I am starting to think is a buffer or an opamp used in your sample-and-hold circuit, since you can not apply a continuous waveform together with a discrete-time signal generated by a SAR register and a DAC to comparator's inputs. If that is the question then it will definitely depend on the S/H architecture that you are using - some of them may relax the specs.

If the question was regarding whether the mentioned opamp can be used as a buffer - yes, it can. I think that that is a good choice in terms of lowered output impedance, if we are considering the topology in general.

If I were you I would have started with designing an opamp in terms of maximizing its' GBW. The larger GBW - more stable the opmap in the follower-configuration. Even if the designed opamp appears to be unsuitable in your applications, you will easily identify what you are missing - gain, unity gain freq, settling time etc, and after that find a topology or a solution that helps to improve the parameters you need. It is relatively easy to re-build an opamp when you know technology limitations with "canonical" topologies.

 

[D.A.(Tony)Stewart]

hello
I am trying to design an input buffer for input driving of a SAR ADC.
Is it ok to use a huising amp which is a rail to rail amp?
Please help me what circuit is usually used.

It seems you are citing a reference from a book which ought to explain the reasons for a given design by Mr Huijsing. The comparator BW certainly needs to be >N (bits) times the signal BW but the buffer does not. It just needs to “buffer” the signal BW with a low enough impedance such that the S&H charge current settles before the ADC starts conversion.

There are Track & Hold types, Sample & Hold types and others. The spec for the buffer is either current limited or RdsOn limited to a charge C. For a settling error = 1/2 bit resolution the Tau=RC and the buffer is modelled by some low resistance R (open loop) a 10 bit resolution needs T(settle)=log 2 * (N+1) * Tau settling time. But you could use T= N*tau for <<1/2 bit error.
Minimum C then depends on the leakage RC= time constant to not decay during the conversion time .If ceramic caps are used only NP0/C0G types are chosen to avoid hysteresis error effects from high density ceramics.

But the buffer S&H circuit show requires special timing to perform the differential sample with phi 1e. and then hold switching off and enabling Vcm to ensure the bias is in the linear middle range uses a silicon capacitance with low leakage interfaces.

 

[the8thhabit]

Thanks for your help.
The papers I've seen say that the input buffer should have a bandwidth that is a multiple of the input bandwidth, as shown in the picture.
The sampling rate in the paper is 35MS/s.
Here it says that it should have a large bandwidth of 700MHz, how should I understand this part?

 

[D.A.(Tony)Stewart]

That includes the sample and hold which must be mucho faster than the signal