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ADC INL and DNL plots

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Analogworld

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inl plots

Does anyone has a matlab script that is used to plot the DNL and INL of an ADC (Histogram approach with sine wave input)? There is a such matlab script posted in MAXIM's website. However, the plots looks very bad even with an ideal ADC. So, I suspect that the code is not written very well. Can anyone help? Thanks in advance.
 

inl best fit

Not for matlab, but I write this script on verilog-a for inl dnl measure component
(Sorry, I cann't make attach :)
// VerilogA for TEST_ADC, inldnlmeasure, veriloga
// $Date: 2005/11/25
// $Revision: 0.0 $
// Static perfomance ADc mesure
// Accuracy depend from dLSB=S*T/LSB
// S -slope of ramp
// T - clock signal period
// LSB - voltage of LSB
// Thow methods of INL measure
// method = 0 - End Point INL
// method = other - Best Fit INL

`include "constants.vams"
`include "disciplines.vams"

`define HIBIT 7
`define HIBIN 1023

module inldnlmeasure (vd,inp,inn);
input [`HIBIT:0] vd;
input inp, inn;
electrical [`HIBIT:0] vd;
electrical inp, inn, vclk;

parameter real vtrans_clk = 2.5; // Threshold
parameter real fullscale = 1.0; // For Gain Error Estimation
parameter integer maxcode = pow(2,`HIBIT); // Number of bins
parameter integer method = 0; // 0 - End Point INL; other - Best Fit INL

real X[`HIBIN:0],Y[`HIBIN:0],dnl[`HIBIN:0],inl[`HIBIN:0];
integer maxcount,count,i;
real measbin,offseterr,gainerr,dnlmax,dnlmin,inlmax,inlmin;
integer dnlout,inlout;
real S,S1,S2,S3,S4,D,D1,D0,A1,A0;

analog begin
@(initial_step) begin
for (i=0;i<`HIBIN;i=i+1) begin
X = 0;
Y = 0;
dnl = 0;
inl = 0;
end
count = 0;
dnlout = $fopen("~/dnlmeasure.dat");
inlout = $fopen("~/inlmeasure.dat");
end

@(cross(V(vd[0]) - vtrans_clk, 0)) begin
X[count] = $abstime;
Y[count] = V(inp,inn);
count = count + 1;
end

@(final_step) begin
maxcount = count;
// Linear Approximation (Best Fit)
S1 = 0; S2 = 0; S3 = 0; S4 = 0;
for (i=0;i<maxcount;i=i+1) begin
S1 = S1 + pow(X,2);
S2 = S2 + X;
S3 = S3 + X*Y;
S4 = S4 + Y;
end
D = S1*maxcount - pow(S2,2);
D1 = S3*maxcount - S2*S4;
D0 = S1*S4 - S2*S3;
A1 = D1/D;
A0 = D0/D;
// LSB Estimation
for (i=1;i<maxcount;i=i+1) begin
S = S + (Y - Y[i-1]);
end
measbin = S/(maxcount - 1);
// Offset, Gain Error Estimation
offseterr = -A0/measbin;
gainerr = (fullscale - maxcode*measbin)/measbin;
// DNL, INL estimation
dnlmax = 0; dnlmin = 0; inlmax = 0; inlmin = 0;
for (i=0;i<=maxcount;i=i+1) begin
// DNL
if (i == 0 || i == maxcount) dnl = 0;
else dnl = (Y-Y[i-1])/measbin-1.0;
if (method == 0) begin
// End points INL
if (i == 0) inl = 0;
else inl = inl[i-1]+dnl;
end else begin
// Best fit INL
if (i == maxcount) inl = 0;
else inl = ((measbin*(i+1.0/2.0)+A0) - Y)/measbin;
end
// Summary
if (dnl>dnlmax) dnlmax = dnl;
if (dnl<dnlmin) dnlmin = dnl;
if (inl>inlmax) inlmax = inl;
if (inl<inlmin) inlmin = inl;
// Write for drawing
$fdisplay(dnlout,"%d\t%10.6f",i,dnl);
$fdisplay(inlout,"%d\t%10.6f",i,inl);
end
$fclose(dnlout);
$fclose(inlout);
// Summaries
$display("Summmary of ADC Static Parameters");
$display("Measure Module:\t%m");
$display("Number of Codes:\t%d",maxcount+1);
$display("Max Offset Error:\t%+.2f",offseterr);
$display("Max Gain Error:\t\t%+.2f",gainerr);
$display("Max DNL:\t\t%+.2f/%+.2f",dnlmin,dnlmax);
$display("Max INL:\t\t%+.2f/%+.2f",inlmin,inlmax);
$display("Plot dnlmeasure.dat & inlmeasure.dat for details...");
end
end
endmodule
`undef HIBIT
 

inldnl.m

Maybe you should discuss which part of the code is bad, because Maxim will not simply publish code which are bad for their customer to use and test their ADC on.
 

dnl histogram for(i

Analogworld said:
Does anyone has a matlab script that is used to plot the DNL and INL of an ADC (Histogram approach with sine wave input)? There is a such matlab script posted in MAXIM's website. However, the plots looks very bad even with an ideal ADC. So, I suspect that the code is not written very well. Can anyone help? Thanks in advance.

the number of the codes should be huge. if not, it does not work well.
 

adc threshold error dnl inl

where is the script at MAXIM?
 

dnl code density

Code Density Testing is a matter of somewhat mature method,
and I too agree that Maxim's Code will work.
But as was told by renwl, the number of the samples should be huge, basically about 4 million for 12 bit ADC
 

dnl inl adc

Hello Denismark. Can u give the example of ur inl.dat ? Want to see the dat format ?
How do u output dat in hspice ?

Regards.
 

basic method to determine inl and dnl

I don't have example of inl.dat because I do this a lot of time ago. This file has text format and as u can see from my code it is formed by lines:
// Write for drawing
$fdisplay(dnlout,"%d\t%10.6f",i,dnl);
$fdisplay(inlout,"%d\t%10.6f",i,inl);

this means output e.g.:
0 0.2e-1
1 1.3e-2
2 -2.3e-3

I worked with spectre. This file is formed by verilog-a component. So if hspice support verilog-a that there are no problem occured.
 

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