cmos image sensor sar adc
There are many things to consider when designing ADC for CMOS image sensors. E.g.
1. With the column parallel architecture you will not have one converter you will have 4000 (or 8000 if placed at top and bottom). Each ADC will have its own transfer curve and, thereby, its own INL and DNL curves. Variations in transfer curves between the ADCs can be characterized as fixed pattern noise (FPN).
2. A cmos image sensor has low noise for weak signals but high noise for high signals (due to photon shot noise and pixel FPN). With a 12b conversion pixel FPN and temporal noise can be around maybe 30 LSB or so for high signals.
3. The pixels are not very linear due to the charge to voltage conversion and the source follower. The INLmax from the pixel may be around 1% of the swing, which means around 40 LSB with a 12b converter.
2 and 3 should be used when designing the ADC.
4000x3000 pixels at 200fps and 12b ADC seems challenging! SAR is fast but you might get problems with 12b. Have you considered a simultaneous multislope converter with fast pseudo conversion (**broken link removed**). Please read section 3 in the paper, it is about ADC characterization for image sensors.
I haven't read the book CMOS Data converters for Communications, but I have had Gustavsson as a teacher and I have worked with the co-author Jacob Wikner. I guess the book ought to be good.