syedshan
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What are these Sudden Jerks or Instant rise or Falls... Is it because of sampling frequency bei
Looks like data corruption or misinterpretation around zero - what is the ADC?
Looks like incorrect timing in signal processing.
What type of circuit construction are you using for the ADC?
How are you generating a 250MHz clock?
Yes and no. The low jitter clock is required to fully utilize the ADC performance at higher signal frequencies. Usually, only a low jitter crystal oscillator as clock source will give sufficient low jitter, FPGA PLLs and similar "digital" clock sources are missing the jitter requirements by at least one order of magnitude.You also need a very low jitter clock for this chip. Less then 0.2 psec which is a very clean clock.
I'm tempted to ask in return: How do you know that the LVDS decoding and succeeding data path timing of your design is correct at all? There are many ways to mix up the ADC data by timing violations in digital design.I could not understand what do mean by that.
Where do the specs indicate it may operate at any frequency other than 250 MHz ?
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