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UWB mean >500MHz bandwidth. So for a ZeroIF receiver about 600-800MHz sampling frequency. A pipeline ADC need charge storage. The critical point is that charge processing circuits are inherent slower because they require some OpAmp architecture to transfer charge and settle within some time. I expect that low bit Flash-ADC is the right choice.
Flash is definitely good.....but for higher resolution it is bulky.....the substitute is 2-step flash or folding-interpolating...this time people r using folding-interpolating.....u can check out the following references.....
1. An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology
Vessal, F.; Salama, C.A.T.;
Solid-State Circuits, IEEE Journal of
Volume 39, Issue 1, Jan. 2004 Page(s):238 - 241
Digital Object Identifier 10.1109/JSSC.2003.820867
Summary: This paper deals with the design and implementation of an 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter (ADC) using a SiGe technology with a unity gain cutoff frequency f/sub T/ of 47 GHz. The high-speed high-resolution ADC has .....
AbstractPlus | References | Full Text: PDF(416 KB) IEEE JNL
2. An 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter
Wei An; Salama, C.A.T.;
Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European
19-21 Sept. 2000 Page(s):228 - 231
Summary: This paper deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5µm self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency f.....