module t1 (
input clk,
input reset,
input start,
output sclk,
output sdata,
output ss_n,
output ctrl
);
reg sclk_r;
reg sdata_r;
reg ss_n_r;
reg ctrl_r;
reg [4:0]counter;
reg [7:0]data_counter;
reg flag;
reg even;
reg [63:0] data;
reg [64:0] data_en;
reg i;
assign sclk=sclk_r;
assign sdata=sdata_r;
assign ss_n=ss_n_r;
assign ctrl=ctrl_r;
always @ (posedge clk or posedge reset) begin
if ( reset) begin
flag <= 1'b0;
counter <= 5'd0;//counter to set baud rate at 1Mhz
i <= 1'b0;
ctrl_r <= 1'b0;
sclk_r <= 1'b1;
even <= 1'b0;
data_counter <= 'h0;
data <= 64'h0ff3ffffcfbad000;
ss_n_r <= 1'b1;
data_en <=65'h00000ffff00000000;
end
else begin
if ( start && ~i )
flag <= 1'b0;
else if ( data_counter == 8'd128 ) begin
flag <= 1'b1;
i <= 1'b1;
end
if ( start )
counter <= 5'd0;
else if ( counter == 5'd25 )
counter <= 5'd0;
else
counter <= counter + 1'b1;
if ( data_counter == 8'd130 && i == 1'b1 )
ctrl_r <= 1'b1;
else if ( data_counter == 8'b131 )
ctrl_r <= 1'b0;
if ( counter == 5'd25 && flag == 1'b1 )
sclk_r <= ~sclk_r;
else if ( ~flag )
sclk_r <= 1'b1;
if ( counter == 5'd20 )
even <= ~even;
if ( counter == 5'd25 && (flag || i ) )
data_counter <= data_counter + 1'b1;
if ( flag && ( counter == 5'd24 ) && ~even )
sdata_r <= data[63];
if ( flag && ( counter == 5'd01 ) && ~even ) begin
data <= { data[62:0], data[63] }
data_en <= { data_en[63:0] , data_en[64] };
end
if ( flag && ( counter == 5'd10 ) && ~even )
ss_n_r <= data_en[64];
else if ( data_counter == 8'd129 )
ss_n_r <= 1'b1;
end //if
end //always
endmodule