active-low or active-high

[vaf20]

which one is better in designs as a synthesis view?
suppose we have a block that several output internal net drive theother input internal net .
what should i define output internal nets , active-low or active-high ?
merci
vaf20

 

[jako123]

hi,

dy default you should use active high!!!

only in special cases -> use active low!


ciao

 

[Edward_2288]

hi it is just a matter of reference, which one u prefer. but generally, ppl use positive logic convention (active high).

 

[Big Boy]

Inside an FPGA for example, you can use either of them, as you wish. But when working with decrete components, like 74... chips, most of those use active-low controls.

The reason for doing so is that you can use pull-up resistor, so if the driver of that line go to high impedence, the pull-up will set the input to a logic '1' (deasserted).

 

[yjkwon57]

Actually, there is no difference between them. It is a point of view on logic, i.e., it just depends on which level is treated as logical true. But, some boolean logic can be easily implemented by using active-high logic, some other easily by using active-low logic. I think there should exist both logic in a functional block for optimization. Accoding to the application, the designer will determine which part is implemented active-high or active-low logic.

 

[maharshi_qis]

Generally we prefer active high ...bcoz we need some inverter ckt to get compliment of a signal so as to use active low..

 

[yjkwon57]

Inherently, we use NAND and NOR rather than AND and OR so as to optimize the size and speed. Therefore, using active-high and active-low logic alternatively is ideal!

 

[nandhu015]

Hai

I prefer active low because to avoid induced signal by motors or heavy voltage devices

Nandhu

 

[jinal patel]

active low means digitally if you apply 0(zero) then it works as 1(High) and if you apply high then it works as low. active low mean active when apply low.
and active high means normal. if you apply high then works as high otherwise low