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active load differential amplifier

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alizadeharand

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I just simulated an active load differential amplifier and i got this result for m1 and m2 current versus differential input voltage:

78_1326194710.png

11_1326194710.jpg

71_1326194710.jpg


why does the current behave like this?
 

I don't think any problem in current graph. Summation of both the probe current at any time is equal.
Anyway I did not get your question clearly. Please elaborate it.
 

can you post device dimensions. It seems as though some of the transistor is in linear region.
 

Why you think , both the current should me symmetric? it depends on the differential inputs.
If Input voltage at M1 is high, current at M1 drain will dominate and vise versa.

If you are pointing first graph posted by you, there is problem in the current sink biasing. ( because sum of both the currents are not equal).
Again, since this is single ended output, current waveforms may not be symmetric. ( but yes their summation should be equal)
 

as vin1 goes more negative than vin2, we have this problem, but as vin1 goes more positive than vin2 we dont have this problem. what is the reason?
 

M3 creates Output common mode, When it is biased properly, CM is maintained. when you try to reduce Vin1 current always try to maintain the same. Even you increase Vin2 with large step, your change in current in non linear. Current in M4 tries to follow the reference current.
 

Hi varun,
I agree, M4 always follow M3. But when vin2 increses by more than 2-3 overdrive voltages(after which it enters linear region), almost all the current will flow through M2. But until then it should be a linear increse in current. Correct me if I'm wrong.
 

But when vin2 increses by more than 2-3 overdrive voltages(after which it enters linear region), almost all the current will flow through M2.
Until M1 is off , your all current can't flow from M2.
Need to understand that this is single ended output, M1-M3 are not exactly the same as M2-M4. And thats why even for a very small increase in Vin1 from Vin2 will give you Vout = high, but in reverse Vin2>>VIn1 will not make Vout = low.
This means linearity of the device is very small in few millivolts to tens of millivolts.
 

so can you explain what exactly happen when vin1 goes less than vin2 ?

i think it must be like this:
when vin1 >> vin2 :
m2 -> off and and all current will flow through m1 and m3. due to vgs3, m4 can not be off and operate in deep triode. so vout goes high.

but when vin2>>vin1:

m1-> off and so m3:eek:ff and -> m4:eek:ff and therefore vout must be low. and all current must flow throw m2.


what is wrong in this analysis?
how the current flow when vin1 >> vin2?
 

but when vin2>>vin1:

m1-> off and so m3:eek:ff and -> m4:eek:ff and therefore vout must be low. and all current must flow throw m2.
When M3 drain voltage starts to increase@drain current decrease, M4, drain current also starts to decrease even though you have large Vin2. And when you have M3 current 0 your M4 drain current will also zero and Vout will be Low.
 

what about M2?
what will happen to the current?
 

It will decay ,thats why I told there will be problem in current sink performance.
It will not get the path to current source.
 

Hi varun,
I agree.. Sry for looking at in fully differential mode.
 

what will happen to m2 current?
what is it shape?
 

In a short, the results from post #1 are indicating unsuitable circuit bias. For vx=0, it's apparently almost in saturation. The exact condidtions aren't reported, so we need to guess e.g. about input common mode voltage. It's also unclear, if the differential input is applied single ended or differentially.

You can easily achieve clarity about the circuit behaviour by watching all node voltages.
 

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