--and_tbench.vhd
entity tb_en is
end tb_en;
architecture tb_ar of tb_en is
component and_gate
port(
A : in BIT;
B : in BIT;
C : out BIT
);
end component;
signal a_i,b_i:bit;
signal out_c:bit;
begin
stimulus: process
begin
a_i <= '0'; b_i <= '0';
wait for 100 ns;
a_i <= '0'; b_i <= '1';
wait for 100 ns;
a_i <= '1'; b_i <= '0';
wait for 100 ns;
a_i <= '1'; b_i <= '1';
wait for 100 ns;
if now = 400 ns then
wait;
end if;
end process stimulus;
add1 : and_gate port map(A => a_i, B => b_i, C => out_c);
end tb_ar;