[SOLVED] Active Filter for PLL

[LvW]

It is approximately 5.2 V

The operating point (biasing) of your loop filter must be selected/designed with respect to the dc input/output requirements:
* nominal input dc voltage - identical to the PFD nominal output voltage;
* nominal output dc level (5.2 volts) - identical to the VCO nominal input voltage.

Remark: Design of the complete loop must consider the inverting characteristic of your filter (as shown in your 1st posting).

 

[kommanche]

The operating point (biasing) of your loop filter must be selected/designed with respect to the dc input/output requirements:
* nominal input dc voltage - identical to the PFD nominal output voltage;
* nominal output dc level (5.2 volts) - identical to the VCO nominal input voltage.

Remark: Design of the complete loop must consider the inverting characteristic of your filter (as shown in your 1st posting).

Thank you,

I will work on it.

 

[tony_lth]

I used to use PLL + AD797A, there should be no problem with AD797A.
Can you paste your ADISimPLL simulation results?
Can you paste your schematics?
There are some special tricky for AD synthesizer, you can try to lock to a higher freq, to see the PLL can work or not.

 

[fred23]

Two things to watch using the AD979A as an active loop filter:

1. The input bias current is high, of the order of 1uA. This will lead to very high reference spurs unless your loop bandwidth is very low. You can simulate this on ADIsimPLL.
2. The input common mode voltage range makes it very difficult to operate with a single supply

Also, the loop filter configuration you have chosen, (in ADIsimPLL called CPA_FBP1PF) exposes the op amp to very short current pulses from the phase detector, and you may be better with something like CPA_PPFil. Both should lock, but the one with prefiltering keeps the op amp a little happier.

 

[kommanche]

I used to use PLL + AD797A, there should be no problem with AD797A.
Can you paste your ADISimPLL simulation results?
Can you paste your schematics?
There are some special tricky for AD synthesizer, you can try to lock to a higher freq, to see the PLL can work or not.

Hi,

I attached my circuit. Output is always pushed to ((Vss-)+1.5V). In my case Vss- is GND. By the way I am sure that my synthesizer works correctly.

Regards,

View attachment untitled.bmp

 

[tony_lth]

What is the voltage of "Vr" in your sch?
I suggest you use the value of ADISimPLL suggested:
C3=48.9nF/R2=58.2/C2=1.32uF/R3=1K/C4=9.8nF
And I suggest you change the topology of PLL from CPA_FBP1PF to CPA_PPFil, R1//C1 filter is important.

 

[kommanche]

What is the voltage of "Vr" in your sch?
I suggest you use the value of ADISimPLL suggested:
C3=48.9nF/R2=58.2/C2=1.32uF/R3=1K/C4=9.8nF
And I suggest you change the topology of PLL from CPA_FBP1PF to CPA_PPFil, R1//C1 filter is important.

Vr is approximately 2.5 V. I tried a split supply case but It is very strange that output is always pushed to ((Vss-)+1.5V). Will changing the topology correct this?

By the way what if I use a standard opamp low pass filter?

 

[FvM]

It is very strange that output is always pushed to ((Vss-)+1.5V).

It's far from being strange. Most likely it's a simple polarity reversal. One week ago, biff44 suggested to change the phase detector polarity, did you ever try? If the polarity is known to be correct, are you sure if the the programmed frequency is within the VCO range?

 

[kommanche]

It's far from being strange. Most likely it's a simple polarity reversal. One week ago, biff44 suggested to change the phase detector polarity, did you ever try? If the polarity is known to be correct, are you sure if the the programmed frequency is within the VCO range?

Yes, it did not work.

The programmed frequency is certainly in the range.

Regards,

---------- Post added at 15:00 ---------- Previous post was at 14:25 ----------

Oh no! I am wrong. You are correct Biff44 and FvM. Problem was just PD polarity error. It is corrected now.

Thanks a lot ..

 

[biff44]

That is too funny!