Accuracy of simulation

[Zarrin]

Can anyone tell me how much difference exist between hspice simulation results and real values? In other words, what is the difference between, for example, the delay of a path in a really fabricated chip with the one obtained by hspice simulation? Is there any reported statistics in this regard? Thanks.

 

[FvM]

You can start with looking at the difference between fast and slow process corner simulations.

 

[Zarrin]

Thanks for the reply. Since i don't have any specific implemented chip to measure the difference, i won't be able to compare fast or slow simulation results with real values. I just want to know to what extent i can rely on simulation results. (e.g. say, simulation results is 90% accurate in comparison with real values on a chip).

 

[FvM]

Fast and slow corner are usually implemented as alternative libraries for a specific process. According to the assumptions, the real chip results should be between both.

 

[saurabhr8here]

The question you're asking is not related to SPICE but more related with the device/interconnect models provided by the foundries. For advanced nodes, depending on your target application (digital, SoC, analog etc.) and the temperature range of operation (typically -40C to 125C) foundries will provide you with temperature accurate transistor models with process variations+statistical variations built in their process development kit. These are basically tolerances, or the range of variation you can expect from a typical semiconductor process. As I mentioned, depending on your target application, you may only care about Ion/Ioff, capacitance variation if you're looking at digital delay chains (critical paths etc.) or you may want accuracy in your models for gm and rout if you're an analog designer. Models are tailored according to application. Additionally, the foundries calibrate the models to match their measurement results from time to time.

As mentioned in the reply above, a lot of the design is done based on corners. The idea is to look at the worst case devices (fast and slow devices) and design keeping in mind the worst case scenario. For example, if you're looking at the delay of your circuit, you'd ensure that it operates at the SS (slow-nmos, slow-pmos) device corner, worst case temperature (typically high temperature, but worst case temperature changes for advanced nodes) and voltage value (VDD-x%) (typically called Process Voltage Temperature, PVT corner). Hence once your chip comes back, it might not have the worst case devices and hence you have a very high probability that you'll get a delay better than you designed for. So, it is not possible to match simulations exactly to real devices, rather it is possible to match them, but process variation is a b**ch and since you can't control it, you learn to live with it and design for the worst case scenario or leave a 'margin' in your design to work with variations.

There is this whole Monte Carlo approach, but then I guess I'd be getting into a longer post/rant and I think unless you're especially interested, the paragraph above and the shorter answer in the previous post should work .