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Accelerating CIFAR-10 on a FPGA

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Full Member level 4
Jun 19, 2014
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I want to accelerate CIFAR-10 dataset on a Virtex 5 FPGA. I think I have built correctly the CNN on VHDL. My question is how I load the dataset on the FPGA? Or should I send the images through another device/laptop on the FPGA? I thought also of using SPI/I2C/UART/Ethernet but seems this makes a bottleneck? Right? Also, could it be better to store the dataset to a HDD and send them directly without the need of using a laptop? Any idea? I have found a few links, however I need speed, as you can understand. Can I use external RAM to load there batch data of the CIFAR-10?
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imho you can use a hard-processor or soft-processor and program it in C/C++ language in order to read images. You can for example use Zynq-700 SOC (hard processor ARM) and program for this hard CPU communication with FPGA by AXI bus. Program you can write in free Xilinx SDK with C++.. Of course you can also use soft-processor for example Microblaze (also program it in C in free SDK). Many depend on your project internal structure. As far as I remember it correctly Keras for example has API functions to load images or datasets. if you don't want to use hard of soft processor, you can also use for example JTAG interface to read images.

Best regards

could you unveil the mystery how you implemented the CNN on VHDL. It might be very interesting for many users of this foorum ;)

Best Regards
I am very specific, on what I am saying. I said "I think".. .From the level "I think" Ι have the code correctly to the level "it works efficiently" is far too much far. I think I need a few weeks/months to have something working properly...
There are online tools for this work, I didn't invent the wheel...
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