[SOLVED] Absolute value of Signed(15 downto 0)

[acoektos]

Hi everyone

Im trying to detect an event from some ADC data based on the Magnitude of a peak in VHDL. This should just be as simple as

signal EVENT_DETECTED : std_logic;
signal INTERNAL_REG_IN : signed(15 downto 0);
signal CLK : std_logic;
signal RST : std_logic;

EVENT_DETECTOR : process(RST,CLK)
if RST = '0' then
  EVENT_DETECTED <= '0';
elsif RISING_EDGE(CLK) then
  if abs(INTERNAL_REG_IN) > 10000 then
    EVENT_DETECTED <= '1';
  else
    EVENT_DETECTED <= '0';
  end if;
end if;

But when I simulate with all data from X"FFFF" downto X"0000" I see a little inconsistency around the shift from -32768 and 32768. At the rising edge when internal_reg_in have value "1000 0000 0000 0001" (-32768) then EVENT_DETECTED signal goes low for one clock cycle (until the internal_reg_in have value "1000 0000 0000 0000" at the rising clock where it goes high again. Last I checked abs(-32768) = 32768 which is much higher than 10000 which should make the EVENT_DETECTED high, so why is it going low in my simulation?

I am using Xilinx ISE and ISim for synthesizing and simulation. I have attached two screenshots of simulation showing the problems I have seen.

Screenshot zoomed into the problem.

Screenshot of all the test from X"FFFF" downto X"0000".

I hope that someone is able to tell me why my simulation shows this behaviour and tell me what I can do to make it accept -32768 as a number for which the absolute value is larger than 10000.

Thanks in advance

 

[TrickyDicky]

It will be because x"8000" = -32768, and the abs value is 32768. This requires 17 bits to represent signed which is 1 more bit than the origional, so the actual value wil return 0 (or maybe even x"8000", as actual required value is x"08000"), which is < 10000. Try this instead:

if abs( resize(INTERNAL_REG_IN,17) ) > 10000 then

 

[acoektos]

Thank you very much. That helped me a lot. Totally logical, however, not something I were aware of before.