About Xilinx Virtex2 Global clock pins

[PeterChow]

xilinx cpld global clock

Hi
I have got a problem during my desing process,It is about Virtex2's global clock pins.
In it's datasheet there are expressions like this:
-----------------------------------------------------------------------------------------------
The primary (GCLKP) and secondary (GCLKS) clock pads have no relationship
with the P-side and N-side of differential clock inputs. In banks 0 and 1, the GCLKP
corresponds to the N-side, and the GCLKS corresponds to the P-side of a differential clock input. In banks 4 and 5, this correspondence is reversed.
-----------------------------------------------------------------------------------------------
Now I must get differential clock output (signals: lvpecl_clk_n and lvpecl_clk_p) from Virtex2,so how should I connect the differential pins?I am puzzled with the expressions.
Suppose it is in Bank0,the differential signal lvpecl_clk_n should be GCLKP or GCLKN?

Thanks

Added after 26 minutes:

I am afraid I made a mistake,when it is used as global clock path,the direction of the global clock pins are input.So if I wanna a lvpecl differential clock from them,they can just be viewed as normal IO pins.So the P-side of pins should be connected to the P-side of the signal,and so as the N-side pins and signals.It is?Thank you.

 

[echo47]

clock pins pld

That's confusing. Can you simplify your question?

With an LVPECL output, I don't think it matters if its a clock or not, or which pair of pins you choose. You can use global clock pins as general purpose outputs. Do you see anything wrong with simply instantiating an OBUFDS_LVPECL_33, and then connecting it to the desired pair of pins? Like this in Verilog 2001:

module top (INp, INn, OUTp, OUTn);     // device is 2v80-4-cs144
  (* LOC="B6" *) input  INp;
  (* LOC="C6" *) input  INn;
  (* LOC="D7" *) output OUTp;
  (* LOC="A6" *) output OUTn;
  wire data;

  IBUFDS_LVPECL_33 in1  (.I(INp), .IB(INn), .O(data));
  OBUFDS_LVPECL_33 out1 (.I(data), .O(OUTp), .OB(OUTn));
endmodule

Those are all global clock pins in bank 0. The results look fine in FPGA_Editor.

 

[tlp71@hotmail.com]

instanting differential pin xilinx

me too think that you can use any pairs of pins that support the standard that you would use. You must be care to use the xxp and xxN pin to drive the positive and negative line.