about wire and reg in instantiation

[wanida]

Hi.
I know that outputs that are in an always block must be declared as "reg" not "wire".
Let's say module A has output outA and outB in an always block therefore they must be declared as "reg".
e.g. module (inA, inB, outA, outB).

My question:
What if the module A is instantiated in another module B and not placed in an always block? Should it be declared as "wire" in module B?

And what if any of the output of the module A is just used internally in the module B that instantiates it, should there be a declaration of reg for that name in module B?

thank you.

 

[tariq786]

its a very good question. I had the same problem.

What you would do is that you would declare it as wire in the module where you are instantiating it. This is how i did. Experiment and let me know.

 

[wanida]

Yes, I declare the outputs as wire in the top module that instantiates the lower module. I find this out by trial and error. I am wondering if there is a clear guideline in any recommended document on this?

Can I instantiate a module within an 'always @ (posedge clk)'?
I tried but couldn't.
So if not, my guess is that it means: if I have several lower modules in a top module clocked design, I should have design all in blocks (submodules) before instantiating them together. Is this correct?

Am I going through what all newbies are going through or am I missing something fundamental?

 

[Shahzad40]

No, you cannot have instantiation in always block. The top level module always consists of several submodules (which are instantiated). The top level module has instantiations and (if required by design) sequential blocks (regions of always block). These instantiations and sequential blocks (if any) are all concurrent to each other.
Regarding your early question. Yes, the rule is that the output could be declared as reg or net internally (in the module) but externally it can only be connected to a net type.
an input port is always a net type and can be connected externally to a reg or net. An inout port can be net type only.
Hope this helps

 

[wanida]

Shahzad... you've summarized it well for me. Very helpful. Thanks.