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about vhdl code for feedback loop

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kannan2590

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I want feedback.png vhdl code for the feedback loop as shown in the attached file.
 

TrickyDicky

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Z is a signal.
input is input to the system
this code is placed inside a clocked process.

Your diagram is a simple accumulator.
 
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kannan2590

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Z is a signal.
input is input to the system
this code is placed inside a clocked process.

Your diagram is a simple accumulator.
You are saying z <= z+input.But there is a unit sample delay in the circuit.So how z will come both the times in z <= z +input.Can you explain it to me clearly with vhdl code?
 

TrickyDicky

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Code:
signal z : unsigned(N downto 0) := (others => '0');

process(clk)
begin
  if rising_edge(clk) then
    z <= z + input;
  end if;
end process;
 

kannan2590

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Code:
signal z : unsigned(N downto 0) := (others => '0');

process(clk)
begin
  if rising_edge(clk) then
    z <= z + input;
  end if;
end process;
I tried this code.But the problem is while testing for continuous input data the output z is showing undefined signal.can you tell me the reason why?

The code that i have written is as below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity integrator is
port(
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(23 downto 0);
dout:eek:ut std_logic_vector(23 downto 0)
);
end integrator;

architecture Behavioral of integrator is
signal ifilterout31:std_logic_vector(23 downto 0):=(others =>'0');
begin

ifilterout31 <="000000000000000000000000";

process(Clk,reset)
begin
if reset='0' then
ifilterout31<="000000000000000000000000";
-- ifilterout32<="000000000000000000000000";

dout<="000000000000000000000000";
elsif clk'event and clk='1' then
ifilterout31 <= (din)+(ifilterout31);
dout <= ifilterout31;
-- ifilterout32 <= ifilterout31;



-- ifilterout32 <= ifilterout31;
end if;
end process ;



end Behavioral;
 

TrickyDicky

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I doubt it's showing U, more Likely X. You've assigned ifilterout31 inside and outside the process, meaning you're driving the signal from two sources (not allowed). Delete the assignement outside the process.

Also - where is your testbench?
 

kannan2590

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I doubt it's showing U, more Likely X. You've assigned ifilterout31 inside and outside the process, meaning you're driving the signal from two sources (not allowed). Delete the assignement outside the process.

Also - where is your testbench?
I tried your method .But even after removing ifilterout31 outside the process.the result is the same red line it is showing i.e U or X.You can try it with a data generator which is constantly generating the data
 

kannan2590

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Post your testbench, then I can check it.
Actually check it with 8 bit input and the output 8 bit.In the code as you have posted keep the N value to be N=8 and try .How to make that red line disappear.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tbfir IS
END tbfir;

ARCHITECTURE behavior OF tbfir IS

signal Clk : std_logic := '0';
signal Xin : signed(23 downto 0) := (others => '0');
signal Yout : signed(23 downto 0) := (others => '0');

constant Clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.fir4tap PORT MAP (
Clk => Clk,
Xin => Xin,

Yout => Yout
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period*2;
Xin <= to_signed(-3,8); wait for clk_period*1;
Xin <= to_signed(1,8); wait for clk_period*1;
Xin <= to_signed(0,8); wait for clk_period*1;
Xin <= to_signed(-2,8); wait for clk_period*1;
Xin <= to_signed(-1,8); wait for clk_period*1;
Xin <= to_signed(4,8); wait for clk_period*1;
Xin <= to_signed(-5,8); wait for clk_period*1;
Xin <= to_signed(6,8); wait for clk_period*1;
Xin <= to_signed(0,8);

wait;
end process;

END;

- - - Updated - - -

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tbfir IS
END tbfir;

ARCHITECTURE behavior OF tbfir IS

signal Clk : std_logic := '0';
signal Xin : signed(23 downto 0) := (others => '0');
signal Yout : signed(23 downto 0) := (others => '0');

constant Clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.fir4tap PORT MAP (
Clk => Clk,
Xin => Xin,

Yout => Yout
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period*2;
Xin <= to_signed(-3,8); wait for clk_period*1;
Xin <= to_signed(1,8); wait for clk_period*1;
Xin <= to_signed(0,8); wait for clk_period*1;
Xin <= to_signed(-2,8); wait for clk_period*1;
Xin <= to_signed(-1,8); wait for clk_period*1;
Xin <= to_signed(4,8); wait for clk_period*1;
Xin <= to_signed(-5,8); wait for clk_period*1;
Xin <= to_signed(6,8); wait for clk_period*1;
Xin <= to_signed(0,8);

wait;
end process;

END;
Actually check it with 8 bit input and the output 8 bit.In the code as you have posted keep the N value to be N=8 and try .How to make that red line disappear.this above is the test bench that you wanted.
 

TrickyDicky

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THis is not the testbench for the code you have already posted.
You posted the code for the integrator, this is the testbench for the FIR.
You either need to post all of the code or post the testbench for the integrator.
 

kannan2590

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THis is not the testbench for the code you have already posted.
You posted the code for the integrator, this is the testbench for the FIR.
You either need to post all of the code or post the testbench for the integrator.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY intetb_vhd IS
END intetb_vhd;

ARCHITECTURE behavior OF intetb_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT integrator
PORT(
clk : IN std_logic;
reset : IN std_logic;
din : IN std_logic_vector(8 downto 0);
dout : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;

--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL din : std_logic_vector(8 downto 0) := (others=>'0');

--Outputs
SIGNAL dout : std_logic_vector(23 downto 0);
constant Clk_period : time := 10 ns;


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: integrator PORT MAP(
clk => clk,
reset => reset,
din => din,
dout => dout
);

Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period*2;
Xin <= to_signed(-3,8); wait for clk_period*1;
Xin <= to_signed(1,8); wait for clk_period*1;
Xin <= to_signed(0,8); wait for clk_period*1;
Xin <= to_signed(-2,8); wait for clk_period*1;
Xin <= to_signed(-1,8); wait for clk_period*1;
Xin <= to_signed(4,8); wait for clk_period*1;
Xin <= to_signed(-5,8); wait for clk_period*1;
Xin <= to_signed(6,8); wait for clk_period*1;
Xin <= to_signed(0,8);

wait;
end process;

END;

This above code is the test bench for integrator.
 

TrickyDicky

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Now you're just modifying the first testbench. (I can tell, because this one has some glaring errors).

I suggest you run the testbenches yourself before posting here.
 

lucbra

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TrickyDicky is really patient - or has nothing else to do
 

mrflibble

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I could not understand what is Z and input.can you explain it with vhdl code?
I commend TrickyDicky for his patience. Well done sir!

May I suggest a good book on control theory? Either that or a math book covering Laplace and Z transforms. I suspect that control theory is going to be easier in general. "Signals and systems" by Oppenheim, Willsky, etc chapter 10. There we go.
 
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kannan2590

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Now you're just modifying the first testbench. (I can tell, because this one has some glaring errors).

I suggest you run the testbenches yourself before posting here.
can you explain me what was the error you faced to me because i did not face such problem

- - - Updated - - -

Now you're just modifying the first testbench. (I can tell, because this one has some glaring errors).

I suggest you run the testbenches yourself before posting here.
can you explain me what was the error you faced to me because i did not face such problem
 

kannan2590

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For a start, Xin is not declared.
Actually din int the test bench code is xin.If there is problem in declaration of xin then tell me how to declare xin.Is the feedback circuit is creating problem?Is there any problem in the code of the feedback loop?
 

TrickyDicky

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I suggest finding a good VHDL tutorial and working your way through it. You clearly have no idea what you're doing.
 

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