about vhdl code for division and multyplying

[Cutey]

about vhdl

hii all
if there is any one tell me how we can program a code in vhdl for sivision and multyplying without using (*) and (/)??
thankd in advance

 

[shitansh]

Re: about vhdl

hi,

By shifting databit right once you will get multiply by 2, and by shifting data left once you will get divide by 2.

Also multiplication is nothing but sucessive addition and division is nothing but sucessive subtratction, this also you can use.

HTH,
--
Shitansh Vaghela

 

[Cutey]

about vhdl

i know about shifting and also can make it by concatination using & ..but how can we know the variables as an example we have a and b so how we know that a need 2 shift and so... i need the algorithm for it

 

[shitansh]

Re: about vhdl

hi,

For multiplication, as i told you erlier use sucessive addition.
e.g 3x4= 3+3+3+3 = 12

Likevise for division you can use sucessive subtratction.

HTH
--
Shitansh Vaghela

 

[Cutey]

Re: about vhdl

i programmed the fllowing code it is crrect but get wrong result

the fllowing code is shif multiplying
please if any one can tell me it get wrong result?


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MUL is
Port ( clk : in STD_LOGIC;
-- i:in integer:=1;
result : out STD_LOGIC_vector(15 downto 0);
m : in STD_LOGIC_vector(7 downto 0);
n : in STD_LOGIC_vector(7 downto 0);
start:in std_logic);

end MUL;

architecture Behavioral of MUL is
signal count:integer:= 0;
signal n1,m1:std_logic_vector(7 downto 0);
signal result1:std_logic_vector(15 downto 0);
begin
process(clk)

begin
m1<=m;
n1<=n;
--result<=result1;

if (rising_edge(clk))then
if( start = '1' )then
result<="0000000000000000";
count <=0;
else
if (count /= 8 )then
if (m1(0)='1')then
result<=result1+n;
end if ;
n1 <=n(6 downto 0) & '0';
m1 <='0'& m (7 downto 1);
count <=count+1;
end if ;
end if;
end if ;
end process ;

end Behavioral;

 

[Cutey]

please ppl help meeeeeeee

 

[sriram317]

JUST AN EXAMPLE
BUT WORKS PERFECTLY



library ieee;
use ieee.std_logic_1164.all;

entity division is
port ( a : in integer range 0 to 255;
b : in integer range 0 to 17;
quo : out integer range 0 to 17);
end division;

architecture structure of division is

begin
process(a,b)
variable var : integer range 0 to 255;
variable count,i : integer range 0 to 127;

begin
i:=0; var:=a;count:=0;
for i in 127 downto 0 loop
if (var>=b) then var :=var-b;count:=count+1;
else
quo<=count;exit;
end if;
end loop;
end process;
end structure;

 

[TrickyDicky]

Mine works better:

entity division is
port ( a : in integer range 0 to 255;
b : in integer range 0 to 17;
quo : out integer range 0 to 17);
end division;

architecture structure of division is

begin

process(a,b)
begin
  quo <= a / b;
end process;

 

[sriram317]

mine works better:

entity division is
port ( a : In integer range 0 to 255;
b : In integer range 0 to 17;
quo : Out integer range 0 to 17);
end division;

architecture structure of division is

begin

process(a,b)
begin
  quo <= a / b;
end process;

hahaa... Nice try dude... Butyours wont synthesize in xilinx... Check it out !!

 

[vipinlal]

The below code doesnt use * or / for division between two unsigned numbers.
VHDL coding tips and tricks: A VHDL function for division two unsigned numbers