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About verilogA simulation

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DZC

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Hi,
I create a simple VerilogA model and use it within a transistor level circuit(a simple Inverter),but I found when I add the VerilogA module the simulation process become incredibly slow,and there are some warnnings too.
Anybody having encountered such problem?
Thanks for your reply.
 

elbadry

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perhaps you need a transition filter on your output

V(out) <+ transition( V(x),tdelay, trisefall)

You may also be using an if condition which would slow it down
 

swicap

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u should properly set ur rising/f and cross tolerance time.
 

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