About verilogA simulation

[DZC]

Hi,
I create a simple VerilogA model and use it within a transistor level circuit(a simple Inverter),but I found when I add the VerilogA module the simulation process become incredibly slow,and there are some warnnings too.
Anybody having encountered such problem?
Thanks for your reply.

 

[elbadry]

perhaps you need a transition filter on your output

V(out) <+ transition( V(x),tdelay, trisefall)

You may also be using an if condition which would slow it down

 

[swicap]

u should properly set ur rising/f and cross tolerance time.