about the process for PLL

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gingerjiang

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hi all
i will design a pll.
i want to know if i need a special process for the pll, because the vco will be integrated on the chip.
thanks advance!
 

i think the mixed signal CMOS process will be ok , and should include thick metal for inductor implementation

khouly
 

    gingerjiang

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khouly said:
i think the mixed signal CMOS process will be ok , and should include thick metal for inductor implementation

khouly
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thanks khouly
i use a mixed signal process indeed, but this process don't provide inductor. will i design this inductor and simulator it myself?
 

of course u need to design the inductors by yourself and simulate it , and measure it
but u will need full em simulation to get the best results

and it's preferred that the process contain a thick metal option , and accumulation mode varactors


khouly
 

    gingerjiang

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u can always do ring oscillator

Added after 28 seconds:

if ur phase noise spec aint that tough
 

    gingerjiang

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Dear gingerjiang

what is ur PLL target application ?

FS , CDR , modulation , demodulation , clock sync ,

khouly
 

khouly said:
Dear gingerjiang

what is ur PLL target application ?

FS , CDR , modulation , demodulation , clock sync ,

khouly
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Dear khouly

I want to design a frequency synthesizer, but I am only a beginner.

I find some softwares for inductor calculation, e.g. appcad, spiral etc., but I don't know whether these tools are enough to design an inductor. I have the doubt about these tools that they don't consider all factors.
 

for inductor design , u should use some EM simulator , and model the inductor good , to get all the paracitics , and so on
u can use momentum , Sonnet , HFSS , whatever u want

khouly
 

    gingerjiang

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Hi
Take attention to isolation of analog and digital parts
Dig part produces noise and sfdr of analog parts degrades
 

    gingerjiang

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