kannan2590
Member level 4
- Joined
- Sep 1, 2012
- Messages
- 77
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Location
- india
- Activity points
- 2,321
According to this post the question is for the filter written in vhdl code the multipliers that i have used in the code is 164 multipliers .As per the fpga there are total 192 multipliers But the synthesis report it shows 148 multipliers and the filter coefficients are symmmetrical.I doubt whether during the optimization of the code the it has reduced the no of mutipliers.Will it effect the final result in the hardware.I use virtex 4 fpga and this hardware HAS 192 multipliers totally.The simulation results of the filter code shows correct result.What is your opinion on this reduction in the no of multipliers?