J
jiangwp
Guest
when designing a gate driver of TFT, the high voltage level shift is difficult,
due to the large output channel.
So a small power dissipation level shift is must.
How to design a level shift with little power dissipation is a challenging problem?
Someone has a good ideal ?
due to the large output channel.
So a small power dissipation level shift is must.
How to design a level shift with little power dissipation is a challenging problem?
Someone has a good ideal ?
