threekingtiger
Member level 1

I've seen some file provided by the foundry about the vertical PNP device in CMOS tech. Part of the file data is listed below:
=================================================
TT FF SS
IS 1.19E-18 9.52E-19 1.45E-18
BF 0.9014 1.03661 0.76619
=================================================
I think it is the variation of bjt's base width that results in the deviation from TT corner, i.e., if WB is smaller, the beta(forward active) should be larger, which coordinates with the data above. But could anyone explain for me that why the IS parameter of the TT corner is even larger than that of the FF corner and even smaller than that of the SS corner, considering the fact that the smaller of WB, the larger of IS.
PS: IS=q*A*Dn*ni^2/(WB*Nd) for PNP device
=================================================
TT FF SS
IS 1.19E-18 9.52E-19 1.45E-18
BF 0.9014 1.03661 0.76619
=================================================
I think it is the variation of bjt's base width that results in the deviation from TT corner, i.e., if WB is smaller, the beta(forward active) should be larger, which coordinates with the data above. But could anyone explain for me that why the IS parameter of the TT corner is even larger than that of the FF corner and even smaller than that of the SS corner, considering the fact that the smaller of WB, the larger of IS.
PS: IS=q*A*Dn*ni^2/(WB*Nd) for PNP device