Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

About the corner of BJT

Status
Not open for further replies.

threekingtiger

Member level 1
Joined
Jul 31, 2010
Messages
38
Helped
8
Reputation
16
Reaction score
8
Trophy points
1,288
Activity points
1,564
I've seen some file provided by the foundry about the vertical PNP device in CMOS tech. Part of the file data is listed below:

=================================================
TT FF SS
IS 1.19E-18 9.52E-19 1.45E-18
BF 0.9014 1.03661 0.76619
=================================================

I think it is the variation of bjt's base width that results in the deviation from TT corner, i.e., if WB is smaller, the beta(forward active) should be larger, which coordinates with the data above. But could anyone explain for me that why the IS parameter of the TT corner is even larger than that of the FF corner and even smaller than that of the SS corner, considering the fact that the smaller of WB, the larger of IS.

PS: IS=q*A*Dn*ni^2/(WB*Nd) for PNP device
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,689
Reputation
5,358
Reaction score
2,291
Trophy points
1,393
Location
Germany
Activity points
44,155
Guess the IS values for FF & SS are swapped: IS=1.19E-18 -20% (SS) / +22% (FF)
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,236
Helped
2,117
Reputation
4,238
Reaction score
1,970
Trophy points
1,393
Location
USA
Activity points
58,016
I don't think Is and base width have a strong direct link. And
this is the weakness of the "corner" type model gor analog,
especially if "corners" are really defined based on a non-
BJT device (the FETs). Then "fast" pertains mainly to poly
linewidth (don't care), Tox (don't care) and S/D drive (base
width and Is, likely for different reasons).

Of course with that sweet sub-unity beta the good news
is that you probably don't care because the device is junk.
What you probably do care about is, how good a job did
the foundry do on modeling the aspects of a junk device
that you really care about (low current Vbe vs Ie across
temperature, for bandgaps, most likely).

Anybody who gives you a 3-corner model for analog design
doesn't care if you succeed.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top