about the channel modulation parameter

[urian]

hi ,there
i want to find the channel modulation parameter λ in my process file to calculate the output resistance ro,but i dont know the name of it used in the process.
Then i download the BSIM4 model file and find that the Channel length modulation parameter is called PCLM.but i fail again to find it in my process file.
so anyone who knows the name of λ in common process file?
and how do you calculate the output resistance ro of a transistor?


by the way, the default value of PCLM in BSIM4 model file is 1.3, i think it is so large that i cant believe it is the so-called parameter λ.


regards
minci

 

[leozuo]

lamda?

why dun you just simulate the output resistance?

 

[dedalus]

In BSIM4 model Early voltage (1/λ) is used instead of channel-length modulation parameter. PCML is adjustable parameter, used to compensate for some errors in calculation of Early voltage. See BSIM4 manual (section 5.7.1.). It's virtually impossible to calculate output resistance using BSIM4 model by hand.

If you need to calculate output resistance by hand you can use next method. Determine value of Early voltage (Va) from extrapolated back to Vds axis output characteristics of transistor as shown in the attached figure. Than calculate output resistance using ro=Va/Id. You'll obtain approximate value of ro.

 

[urian]

thanks,dedalus, and leozuo
to calculate gain using gm•(ro1 || ro2),i think,one should know the value of ro.
if not,how do you atttain the gain? just look at the result of simulation?
and i see that there is a ron item in the annotation of DC operating point of transistor,what dose this mean? just the reciprocal of gds,or it is the ro?


to determine the value of VA,we should extrapolate back to Vds axis output characteristics of transistor,then the output characteristics is obtained by simulation or by foundry?

 

[upvl]

hi ,there
i want to find the channel modulation parameter λ in my process file to calculate the output resistance ro,but i dont know the name of it used in the process.
Then i download the BSIM4 model file and find that the Channel length modulation parameter is called PCLM.but i fail again to find it in my process file.
so anyone who knows the name of λ in common process file?
and how do you calculate the output resistance ro of a transistor?


by the way, the default value of PCLM in BSIM4 model file is 1.3, i think it is so large that i cant believe it is the so-called parameter λ.


regards
minci

You can get it by simulation. Today's model is much more complex than what we learn in texts, and some parameters are even without physical meanings.

 

[sutapanaki]

Life would have been so much easier if the above figure was really true for MOS transistors. However, for modern day technologies the extrapolated lines do not cross at the same point. So, Early voltage is kind of meaningless in MOS design. You can always find ro from simulation. The thing is that you don't have to base your design (gain) on knowing the exact value of ro. Which you can not know, anyway. Usually one doesn't design open loop amplifiers where the gain is dependent strongly on ro of the transistors. If you want an amplifier that you'll use in a feedback configuration, then you'll want a large open loop gain and you would not care much about the exact value of that gain.

 

[leozuo]

you can get ro by simulating a single transistor which is biased at right voltages. Since ro is prportionally to L^2/Vds,sat^2, normally, you can change the length of the mosfet and keep the inversion level fixed.

 

[urian]

thans guys.
the problem is that i must design a comparator with open loop pre-amp whose gain is approximately 6 to 8 and bandwidth above 200M.
i give 100uA to the tail current transistor,then the UGW is only 300~400M,so i must control the gain using 0.13u process.

by the way, if i want to simulate the ro,then which parameter represent it? does ron do? cause i dont see ro in the parameter box

 

[sutapanaki]

gds should do the job, it is in the model.
BTW if you need to design a pre-amp for the comparator why don't you load each pre-amp with a resistor? And then to keep the input referred offset below certain limit you just need to guarantee the minimum value of the gain.

 

[urian]

cause i use a dynamic comparator,and i must utilize a clock signal to turn on and off the triode transistor behaving as a resistor load.

and how to test the input referred offset?
i just give the differential input a dc level and to see which value will cause the output to transfer from high level to low or otherwise. then the value triggering the change is the input referred offset.
does this method right?

 

[sutapanaki]

yes, sounds about right. But you need, of course, to do this in Monte-Carlo simulation.
Basically, I would do it like this: since it is a clocked comparator, you only get results at the clock. I'd change the input differential voltage in steps, each step for example of 0.5mV (or whatever you choose). While the input is at a given step, I'd clock the comparator to get the output. I'd extract only this input value for which the comparator changes state. I'd sweep through all input steps for one monte-carlo run. Then I'd sweep again for the next monte-carlo run and so on. This way you get one input value at which the comparator triggers per run. At the end you can do some statistics and see what is the mean and the sigma of your input.

 

[urian]

terrific,sutapanaki,I'll try the Monte_Carlo simulation,cause i am not familar with it,i have to read the manual before.
thanks a lot!

 

[rfsystem]

Also in older mature CMOS processes there is no current independend early voltage or bias independend lamda.

That is because the channel length modulation is defined by the movement of the neutral depletion zone depending on drain voltage. The math description involves a square root function. So the fixed early voltage is an oversimplification. In small MOS devices the calculation of the channel length effect is not 1D but also take 2D effects into account and is integrated in models after BSIM4.

For analog application you probably use longer channels so can work with the 1D depeletion variation as main effect for out current variation. Practical the early voltage defined as crossing point of the tangent to the voltage axis could varies through the drain voltage by a factor 2.