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link_library is the library where components already present in the design can be found. target_library is the library with the components that will be used to synthesize a design. In brief, consider the link_library as the input library and the target_library as the output library. The may or they may not be the same (for example when you want to change the implementation technology).
link_library is the library where components already present in the design can be found. target_library is the library with the components that will be used to synthesize a design. In brief, consider the link_library as the input library and the target_library as the output library. The may or they may not be the same (for example when you want to change the implementation technology).
To explain in a simple way, target library contains the components that you want to "infer", while link library contains the components that you want to "instantiate".
Target library is the ASIC vendor library whose cells are used to generate a netlist for the design described in HDL during synthesis. The HDL code is mapped to cells from this library.
Link library is uesd when the design is already in the form of a netlist or when the source HDL code has cells instantiated from the technology library. Link library indicates to DC, the library in which the descriptions of these cells are available.
Got these explain from "logic synthesis using synopsys",wish it's clear enough
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