pll sigma delta multi bit single loop
yes, I use it for a PLL frequency synthesizer. I have simulated the MASH DSM in modelsim, it's just 3 accumulaors,the input is unsigned number. The result is the same with expected.
But for multi-bit high order DSM, I don't know the input and output are whether signed or unsigned, and for a 3-bit DSM, how to use the 3MSBs as output? I've tried to write some verilog codes, but all the results are wrong. And I can't find any clues.
The input is a fractional number between 0 and 1, but the output may be between -1 and 2, so how to realize it without using float operation? For example , I use 16-bit input as a fraction , after some operations, the result may be 20-bit, so how to use the MSBs as integer output?