About simulating the compiled netilst by Modelsim

[gaom9]

modelsim netlist cell library

Hi,
I met a question about using modelsim to simulate the netlist after synthesis (compiled).
After using the DC for synthesis the design(only compile without DFT or other process), I added the output verilog netlist from DC , the std cell library (tsmc18.v) and the testbench to modelsim to check if the design can keep the functions after synthesis, but it fails, most of the output is "XXXXX".
I use the fm to check if the RTL and the netlist after synthesis equivalent, and it is successful, the two are equivalent. The DC reports no any slacks (no hold fix) and error
Why? Is there anything I should pay attention when simulate this netlist, please?

Can any one give me some advice, please?

Thank you!
Best regards!

 

[shanmugaveld]

modelsim synthesis

check reset values of the signals.
if u have any memory components initialize it....
find the origin of "XXX".
It may be due to TB also bcoz it wont reflect the real delays as HW behaves during timing simulation..
so make the clk delayed in TB..

Best Regards,
Shanmugavel

 

[gaom9]

how to set clock frequency at 100mhz in modelsim

Hi, shanmugaveld
I did not add the std cell delay to the simulation. I just added the compiled netlist, the technique library verilog file and the testbench to modelsim.
When I do such simulation, should I add the sdf (generated from DC) to modelsim to get a right result?
There are many RAMs and ROMs in my design, and the simulation files of the RAMs have been added to the simulation, the ROMs has been initialized with the initialized files generated from Artison tools.
You said "make the clk delayed in TB", does it mean to add some delay in the TB clk? Or to change the frequency of the clk?

Thank you!
Best regards!

 

[WzWzWz]

compiling cell library with modelsim

You need to find the root X where is come from. and the take the specific solution to fix it.
Maybe clk, maybe xfilter, etc.

 

[gaom9]

modelsim clock delay for hold

Thank you, WzWzWz.
You mean I should change the testbench to fix the XXX in the compiled simulation or post-simulation, is that right?
I thought I should add the same testbench to the RTL and compiled simulations and got the same results before, so as the ensure the functions of the design.

Thank you!
Best regards!

 

[shanmugaveld]

maximum clock frequency calculation in modelsim

As said by WzWzWz, there are various reasons, first you need to find the root cause of "XXX'...

if it is because of clock u need to delay the clock no need to change the frequency..

 

[gaom9]

modelsim tsmc18.v

Hi,
I have tried many method to fixed the "XXX", delay th clock, change the reset signal, but the "XXX" is still there. And when I change the clock frequency, the origin of "XXX" will change. and when lower the frequency, the "XXX" will comes late. Frequency = 100M, the "XXX"comes at 24 clocks after reset. Frequency = 50M, the "XXX" comes at about 4500 clocks after reset. The synthesis frequency is 100MHz and there is no slack there, and within these clocks, the results are right.
How can I fix it?

Thank you!
Best regards!