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about porting netlist to tools

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smith_kang

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hi all
i've problem in porting VHDL netlist in encounter.Is VHDl netlist is not portable to these tools.Coz when i convert it to Verilog netlist its working fine.why is this so.Can anybody explain.

thanks in advance
regards
 

omid219

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Most synthesis tools suport writing netlist in verilog or vhdl. Write verilog netlist and use it for encounter.
 

ryang

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When importing into backend tool like SOC encounter, the gatelevel netlist must be physical implementable. Generally, the netlist only contains the reference to the standard cell & macroes.IS NOT all the statement of VHDL or Verilog supported by Backend tool.

For example,a verilog netlist cannot contain assign statement in it.

As to detail, check the tool's error message to debug.
 

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