About MOS layout in 65nm?

[tshiu]

Someone suggest me size finger=2 as unit block for MOS' dimension in 65nm technology, especially for current mirror and differential pair.
It's based on his company's experience, so he doesn't know the reason.
Does any reference can support this concept ?

 

[Teddy]

By setting number of fingers >1 you reduce parasitic capacitances for S/D.

 

[sulabh]

This will help in transistor matching in the device, as these are analog component and generally have sizes greater than the normal matching becomes critical.