about metal width for large dynamic current?

[ken_cn]

Dear All,

Could you tell me how to calculate the metal width for a connection which has a very large peak current during dynamic but a low dc current during static? Since the document from foundry just provides current limits for dc or RMS.
Do you have any equation or paper about this subject?

Thanks in advance!

 

[dgnani]

besides the electromigration limits there are higher current density limits that will simply instantly blow your wire like a fuse, you can look those up on wiki

as of EM for pk currents in absence of indication from the foundry you can be conservative and simply use the average or rms current and stick to the DC or rms limit for it

some foundries indicate a factor ~20 between pk current EM limit and DC limit

 

[erikl]

... some foundries indicate a factor ~20 between pk current EM limit and DC limit

Peak currents in CMOS circuits very often are currents in both directions: charging & discharging currents of caps (clock-trees, for example). In such case, the EM limit shouldn't be far above the DC or rms limit, I guess.

 

[dgnani]

Peak currents in CMOS circuits very often are currents in both directions: charging & discharging currents of caps (clock-trees, for example). In such case, the EM limit shouldn't be far above the DC or rms limit, I guess.

the limit for rms value of the "currents in both directions" will be similar to DC limit but limitof acceptable peak currents will be higher

 

[dick_freebird]

Reversing current also reverses, to some non-unity extent,
the material drift of electromigration. So an AC EM limit is
not infinite, but 10X DC is a conservative rule of thumb. A
single narrow pulse (one time event, like ESD) could go 100X
but you should back up any such figuring with an ohmic
volume adiabatic heating calc and require the risen temp
to remain under the metal liquidus (~600C for aluminum).

1E5 DC, 1E6 AC A/cm2 are good conservative current
densities.

However one thing you do not know without the help of
the foundry or an FA lab, is what the true worst case
cross section is (over-etch, step coverage, film thickness
control limits).

 

[ken_cn]

Thanks all!
Your replies are very useful to me!
And could you lead me to any theoretical calculation or papers?

 

[timof]

Another problem with large and fast dynamic transients is that their magnitude and distribution (over various conductors, vias, etc.) may be determined by distributed RC effects. One needs to do the extraction/simulation in order to find out the "weakest" conductor (resistor) - the one that has the maximum current.

A typical example is the gate network of the large area power MOSFET - a very fast switching of the gate may lead to very high (several amps) gate current (dynamic) that may burn metal routing or vias/contacts, if the gate routing is not done properly.